參數(shù)資料
型號: ADS7864Y/250
廠商: Texas Instruments
文件頁數(shù): 5/27頁
文件大?。?/td> 0K
描述: IC 12BIT 500KHZ 6CH A/D 48-TQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 500k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 50mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 12 個單端,雙極;6 個差分,雙極
產(chǎn)品目錄頁面: 892 (CN2011-ZH PDF)
配用: 296-30697-ND - EVAL MODULE FOR ADS7864M
其它名稱: ADS7864YDKR
www.ti.com
Code (decimal)
8000
7000
6000
5000
4000
3000
2000
1000
0
N
u
m
b
e
r
o
f
C
o
n
v
e
rs
io
n
s
2044
2045
2046
2047
2048
TRANSITION NOISE
DATA
1.4V
Test Point
3k
100pF
C
LOAD
t
R
DATA
Voltage Waveforms for DATA Rise and Fall Times t
R, and tF.
V
OH
V
OL
t
F
ADS7864
SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005
When the input is differential, the amplitude of the
input is the difference between the +IN and –IN input,
or: (+IN) – (–IN). The peak-to-peak amplitude of each
input is ±1/2V
REF around this common voltage. How-
ever, since the inputs are 180° out of phase, the
peak-to-peak amplitude of the differential voltage is
+V
REF to –VREF. The value of VREF also determines
the range of the voltage that may be common to both
inputs (see Figure 22).
In each case, care should be taken to ensure that the
output impedance of the sources driving the +IN and
–IN inputs are matched. Otherwise, this may result in
offset error, which will change with both temperature
and input voltage.
The input current on the analog inputs depend on a
number of factors: sample rate, input voltage, and
source impedance. Essentially, the current into the
Figure 23. Histogram of 8,000 Conversions of a
ADS7864 charges the internal capacitor array during
DC Input
the sampling period. After this capacitance has been
fully charged, there is no further input current. The
source of the analog input voltage must be able to
charge the input capacitance (15pF) to a 12-bit
settling level within two clock cycles. When the
converter goes into the hold mode, the input im-
pedance is greater than 1G
.
Care must be taken regarding the absolute analog
input voltage. The +IN and –IN inputs should always
remain within the range of GND – 300mV to VDD +
300mV.
Figure 23 shows a histogram plot for the ADS7864
following 8,000 conversions of a DC input. The DC
input was set at output code 2046. All but one of the
conversions had an output code result of 2046 (one
of the conversions resulted in an output of 2047). The
histogram reveals the excellent noise performance of
Figure 24. Test Circuits for Timing Specifications
the ADS7864.
13
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