參數(shù)資料
型號(hào): ADS7846
元件分類: 通用總線功能
英文描述: CMOS 8-Stage Presettable 8-Bit Binary Synchronous Down Counter 16-TSSOP -55 to 125
中文描述: 觸摸屏控制器
文件頁(yè)數(shù): 14/23頁(yè)
文件大?。?/td> 520K
代理商: ADS7846
ADS7846
SBAS125H
14
www.ti.com
16 Clocks-per-Conversion
The control bits for conversion n + 1 can be overlapped with
conversion n to allow for a conversion every 16 clock cycles,
as shown in Figure 10. This figure also shows possible serial
communication occurring with other serial peripherals be-
tween each byte transfer from the processor to the converter.
This is possible provided that each conversion completes
within 1.6ms of starting. Otherwise, the signal that is cap-
tured on the input sample-and-hold may droop enough to
affect the conversion result. Note that the ADS7846 is fully
powered while other serial communications are taking place
during a conversion.
Digital Timing
Figures 9, 11, and Table VI provide detailed timing for the
digital interface of the ADS7846.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ACQ
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
BD
t
BDV
t
BTR
Acquisition Time
1.5
μ
s
ns
DIN Valid Prior to DCLK Rising
100
DIN Hold After DCLK High
10
ns
DCLK Falling to DOUT Valid
200
ns
CS
Falling to DOUT Enabled
200
ns
CS
Rising to DOUT Disabled
200
ns
CS
Falling to First DCLK Rising
100
ns
CS
Rising to DCLK Ignored
0
ns
DCLK High
200
ns
DCLK Low
200
ns
DCLK Falling to BUSY Rising
200
ns
CS
Falling to BUSY Enabled
200
ns
CS
Rising to BUSY Disabled
200
ns
TABLE VI. Timing Specifications (+V
CC
= +2.7V and Above,
T
A
=
40
°
C to +85
°
C, C
LOAD
= 50pF).
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
11
DOUT
BUSY
DIN
10
FIGURE 11. Detailed Timing Diagram.
FIGURE 10. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
1
DCLK
CS
8
1
11
DOUT
BUSY
S
DIN
Control Bits
S
Control Bits
10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
1
1
8
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