參數(shù)資料
型號： ADS7833N
英文描述： 10-Channel, 12-Bit DATA ACQUISITION SYSTEM
中文描述： 10通道，12位數(shù)據(jù)采集系統(tǒng)
文件頁數(shù)： 4/12頁
文件大?。?/td> 150K
代理商： ADS7833N
ADS7833
4
PIN DEFINITIONS
PIN NO
NAME
TYPE
(1)
DESCRIPTION
1
V
3–4N
AI
Voltage Input, Channel 3, Mux I/P 4,
Negative Side
Voltage Input, Channel 3, Mux IP 4,
Positive Side
Voltage Input, Channel 3, Mux I/P 3,
Negative Side
Voltage Input, Channel 3, Mux I/P 3,
Positive Side
Voltage Input, Channel 3, Mux I/P 2,
Negative Side
Voltage Input, Channel 3, Mux I/P 2,
Positive Side
No Connection
Voltage Input, Channel 3, Mux I/P 1,
Negative Side
Voltage Input, Channel 3, Mux I/P 1,
Positive Side
No Connection
Voltage Input, Channel 2, Mux I/P 1,
Negative Side
Voltage Input, Channel 2, Mux I/P 1,
Positive Side
No Connection
Voltage Input, Channel 2, Mux I/P 2,
Negative Side
Voltage Input, Channel 2, Mux I/P 2,
Positive Side
No Connection
Voltage Input, Channel 2, Mux I/P 3,
Negative Side.
Voltage Input, Channel 2, Mux I/P 3,
Positive Side
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
Test Point 1, Make No Connection
Test Point 2, Make No Connection
Digital Supply Voltage, +5V
Digital Supply Voltage, Ground
Digital Supply Voltage, –5V
No Connection
Serial Digital Output, Channel 2
Serial Digital Output, Channel 3
2
V
3–4P
AI
3
V
3–3N
AI
4
V
3–3P
AI
5
V
3–2N
AI
6
V
3–2P
AI
7
8
NC
V
3–1N
—
AI
9
V
3–1P
AI
10
11
NC
V
2–1N
—
AI
12
V
2–1P
AI
13
14
NC
V
2–2N
—
AI
15
V
2–2P
AI
16
17
NC
V
2–3N
—
AI
18
V
2–3P
AI
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
NC
NC
NC
NC
NC
NC
NC
NC
TP1
TP2
V
DGND
V
NC
S
OUT2
S
OUT3
—
—
—
—
—
—
—
—
—
—
P
P
P
—
DO
DO
35
36
37
S
CLK
CONV
DO
DI
DI
Serial Digital Output, Channel 1
Clock for A/D Converters
Start A/D Converters. When CONV goes to
“0” (low) the next rising edge of CLK
starts the conversion.
Digital Control for Asynchronous Sample
Hold. If signal is “1” (high), signals
are sampled.
Serial Digital Input for Input Control Word
A/D Converters Busy. Busy if signal
is “0” (low).
A Delayed and Truncated Version of
the CLK Signals. It is Delayed 50ns
from the CLK Signal and Stays Low
after 13 DCLOCK Cycles.
38
ASH
DI
39
40
SER
IN
BUSY
DI
DO
41
DCLOCK
DO
42
43
44
45
46
47
48
49
50
51
52
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
1–3P
—
—
—
—
—
—
—
—
—
—
AI
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
Voltage Input, Channel 1, Mux I/P 3,
Positive Side
Voltage Input, Channel 1, Mux I/P 3,
Negative Side
No Connection
Voltage Input, Channel 1, Mux I/P 2,
Positive Side
Voltage Input, Channel 1, Mux I/P 2,
Negative Side
No Connection
Voltage Input, Channel 1, Mux I/P 1,
Positive Side
Voltage Input, Channel 1, Mux I/P 1,
Negative Side
No Connection
No Connection
Output of DAC
Decoupling Point for Internal Reference
Input Pin for External Reference
Ground Pin for External Reference
Analog Supply Voltage, –5V
Analog Supply Voltage, Ground
Analog Supply Voltage, +5V
53
V
1–3N
AI
54
55
NC
V
1–2P
—
AI
56
V
1–2N
AI
57
58
NC
V
1–1P
—
AI
59
V
1–1N
AI
60
61
62
63
64
65
66
67
68
NC
NC
A
OUT
CAP
REF
IN
REF
GND
V
AGND
V
ANA+
—
—
AO
AO
AI
P
P
P
P
PIN NO
NAME
TYPE
(1)
DESCRIPTION
NOTE: (1) AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, P is Power Supply Connection.
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參數(shù)描述
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ADS7834E/250G4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit High Speed Low Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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