
ADS7833
7
FUNCTIONAL DESCRIPTION
(See Figure 1)
ADCs AND PGAs
The ADS7833 contains three signal channels each with a
12-bit analog-to-digital converter output. The ADCs operate
synchronously and their serial outputs occur simultaneously.
(Table VI gives the analog input/digital output relation-
ships). The ADCs are preceded by programmable gain
amplifiers. (Table II gives gain select information). For
channels one and two, the PGAs are effective for all three
analog inputs. For the third channel, only the V
3–1
input is
gain changed by the PGA. Inputs V
3–2
, V
3-3
, and V
3-4
are
connected to ADC
3
at a fixed gain of 1V/V regardless of the
Gain Select value.
SAMPLE HOLDS
The ADS7833 contains seven sample holds. Five of them
(SH
1
through SH
5
) sample simultaneously and have their
sample/hold timing internally synchronized. (The timing is
shown in Figure 2).
Three of the sample holds (SH
1
, SH
3,
and SH
5
) are con-
nected to the input multiplexers so that they can provide
simultaneous sampling for all of their channels inputs. In
addition, SH
2
and SH
4
simultaneously sample the third input
of their channels (V
l–3
and V
2–3
, respectively). This is useful
in motor control applications where V
1-2
and V
l-3
are the
quadrature inputs for one position sensor, and V
2-2
and
V
2-3
are the quadrature inputs for a second position sensor
(see Figure 6). In that application, it is desirable to sample
the quadrature inputs of a given position sensor at the same
time (even though they are converted on successive conver-
sion cycles) (see Table III), so that their values are captured
at the same shaft position.
The ADS7833 also has the capability for limited asynchro-
nous sampling. The sampling of SH
6
and SH
7
is controlled
asynchronously by the control signal ASH (see Table III).
This allows two inputs each on channel 1 and channel 2 (see
Table IV) to be sampled asynchronously from the timing of
the other sample holds. This can be useful in motor control
applications where the two inputs for each channel come
from a position sensor and it is desired to sample based on
position sensor timing rather than system clock timing.
FIGURE 1. Functional Diagram.
SH
1
SH
2
SH
6
SH
7
SH
4
SH
5
2.5V
Ref
SH
3
Input Setup
Register
ADC
3
Control
Logic
ASH
Conv
Sample
V
2-1
V
2-2
V
2-3
2
2
2
V
3-1
V
3-2
V
3-3
V
3-4
2
2
2
2
CAP
REF
IN
V
1-1
V
1-2
V
1-3
2
2
2
2
2
ASH
2
2
2
2
2
2
PGA
3
V
3-2
Through V
3-4
V
3-1
Only
2
2
ADC
2
PGA
2
2
ADC
1
PGA
1
2
2
2
Decoder
DAC
8-Bit
8
2
3
2
S
OUT1
S
OUT2
SOUT
3
SER
IN
A
OUT
ASH
CLK
CONV
BUSY
DCLOCK
2
2
2
Input
Select
Gain
Select
Conv
Conv
Conv
DAC
Input
Ref
Ref
Ref
Ref
2