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參數(shù)資料
| 型號(hào)： | ADS7823EB250 |
| 英文描述： | 12-Bit, Sampling A/D Converter with I2C?? INTERFACE |
| 中文描述： | 12位，采樣A / D轉(zhuǎn)換器，帶有I2C？？接口 |
| 文件頁(yè)數(shù)： | 9/15頁(yè) |
| 文件大?。?/td> | 275K |
| 代理商： | ADS7823EB250 |
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ADS7823
SBAS180B
9
FIGURE 2. Basic Operation of the ADS7823.
SDA
SCL
1
2
7
6
8
9
1
2
3-8
8
9
Slave Address
MSB
Repeated If More Bytes Are Transferred
R/W
Direction
Bit
Acknowledgement
Signal from
Receiver
Acknowledgement
Signal from
Receiver
START
Condition
ACK
ACK
STOP Condition
or Repeated
START Condition
The device that controls the message is called a
“
master.
”
The devices that are controlled by the master are
“
slaves.
”
The bus must be controlled by a master device that gener-
ates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The ADS7823
operates as a slave on the I
2
C bus. Connections to the bus
are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (as shown in
Figure 2):
Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy:
Both data and clock lines remain HIGH.
Start Data Transfer:
A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop Data Transfer:
A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data Valid:
The state of the data line represents valid data,
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. There is one
clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions is not
limited and is determined by the master device. The informa-
tion is transferred byte-wise and each receiver acknowl-
edges with a ninth bit.
Within the I
2
C bus specifications a standard mode (100kHz
clock rate), a fast mode (400kHz clock rate), and a high-
speed mode (3.4MHz clock rate) are defined. The ADS7823
works in all three modes.
Acknowledge:
Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Of course, setup and hold times
must be taken into account. A master must signal an end of
data to the slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master
to generate the STOP condition.
Figure 2 details how data transfer is accomplished on the I
2
C
bus. Depending upon the state of the
R/W
bit, two types of
data transfer are possible:
1. Data transfer from a master transmitter to a slave
receiver.
The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after the slave address
and each received byte.
2. Data transfer from a slave transmitter to a master
receiver.
The first byte, the slave address, is transmitted
by the master. The slave then returns an acknowledge bit.
Next, a number of data bytes are transmitted by the slave
to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end
of the last received byte, a not-acknowledge is returned.
The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
with a STOP condition or a repeated START condition. Since
a repeated START condition is also the beginning of the next
serial transfer, the bus will not be released.
The ADS7823 may operate in the following two modes:
Slave Receiver Mode:
Serial data and clock are received
through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP condi-
tions are recognized as the beginning and end of a serial
transfer. Address recognition is performed by hardware
after reception of the slave address and direction bit.
Slave Transmitter Mode:
The first byte (the slave ad-
dress) is received and handled as in the slave receiver
mode. However, in this mode the direction bit will indicate
that the transfer direction is reversed. Serial data is trans-
mitted on SDA by the ADS7823 while the serial clock is
input on SCL. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
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| ADS7823EB2K5 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit, Sampling A/D Converter with I2C?? INTERFACE |
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| ADS7824P | 制造商:BURR-BROWN 功能描述:IC 12BIT ADC 7824 DIP28 制造商:Texas Instruments 功能描述:IC 12BIT ADC 40KHZ 7824 DIP28 制造商:Texas Instruments 功能描述:IC, 12BIT ADC, 40KHZ, 7824, DIP28 |
| ADS7824PB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Channel 12-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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