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參數(shù)資料
| 型號： | ADS7821U |
| 英文描述： | 16-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| 中文描述： | 16位10ms的采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 280K |
| 代理商： | ADS7821U |
6
ADS7821
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. However,
the output will become active whenever R/C goes HIGH.
Refer to the
Reading Data
section.
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7821 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (5
μ
s max) will initiate a conversion.
BUSY (pin 26) will go LOW and stay LOW until the
conversion is completed and the output registers are up-
dated. Data will be output in Straight Binary with the MSB
on pin 6. BUSY going HIGH can be used to latch the data.
All convert commands will be ignored while BUSY is
LOW.
The ADS7821 will begin tracking the input signal at the end
of the conversion. Allowing 10
μ
s between convert com-
mands assures accurate acquisition of a new signal.
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) LOW for
a minimum of 40ns immediately puts the sample/hold of the
ADS7821 in the hold state and starts conversion ‘n’. BUSY
(pin 26) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be
ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without suffi-
cient time to acquire a new signal.
The ADS7821 will begin tracking the input signal at the end
of the conversion. Allowing 10
μ
s between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table II for a summary of CS, R/C, and BUSY states and
Figures 3 through 5 for timing diagrams.
CS
R/C
BUSY
OPERATION
1
X
X
None. Databus is in Hi-Z state.
↓
0
1
Initiates conversion “n”. Databus remains
in Hi-Z state.
0
↓
1
Initiates conversion “n”. Databus enters Hi-Z
state.
0
1
↑
Conversion “n” completed. Valid data from
conversion “n” on the databus.
↓
1
1
Enables databus with valid data from
conversion “n”.
↓
1
0
Enables databus with valid data from
conversion “n-1”
(1)
. Conversion n in progress.
0
↑
0
Enables databus with valid data from
conversion “n-1”
(1)
. Conversion “n” in progress.
0
0
↑
New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
X
X
0
New convert commands ignored. Conversion
“n” in progress.
NOTE: (1) See Figures 3 and 4 for constraints on data valid from
conversion “n-1”.
Table II. Control Line Functions for “Read” and “Convert”.
FIGURE 1. Basic Operation.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7821
+5V
0.1μF
10μF
+
+
2.2μF
+
+
2.2μF
Convert Pulse
40ns min
5μs max
D4
D5
D6
D7
D2
D1
D0 (LSB)
D3
D10
D9
D8
D11
D12
D13
D14
D15 (MSB)
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADS7822C | 制造商:BB 制造商全稱:BB 功能描述:12-Bit High Speed 2.7V microPower Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7822CIDGKRAN | 制造商:Texas Instruments 功能描述: |
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