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參數(shù)資料
| 型號(hào)： | ADS7820PB |
| 英文描述： | 12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| 中文描述： | 12位10ms的采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 280K |
| 代理商： | ADS7820PB |
6
ADS7820
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7820 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (5.4
μ
s max) will initiate a conversion.
BUSY (pin 26) will go LOW and stay LOW until the
conversion is completed and the output registers are up-
dated. Data will be output in Straight Binary with the MSB
on pin 6. BUSY going HIGH can be used to latch the data.
All convert commands will be ignored while BUSY is
LOW.
The ADS7820 will begin tracking the input signal at the end
of the conversion. Allowing 10
μ
s between convert com-
mands assures accurate acquisition of a new signal.
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) LOW for
a minimum of 40ns immediately puts the sample/hold of the
ADS7820 in the hold state and starts conversion ‘n’. BUSY
(pin 26) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be
ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without suffi-
cient time to acquire a new signal.
The ADS7820 will begin tracking the input signal at the end
of the conversion. Allowing 10
μ
s between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table I for a summary of CS, R/C, and BUSY states and
Figures 3 through 5 for timing diagrams.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. However,
the output will become active whenever R/C goes HIGH.
Refer to the
Reading Data
section.
FIGURE 1. Basic Operation (Byte Low).
CS
R/C
BUSY
OPERATION
1
X
X
None. Databus is in Hi-Z state.
↓
0
1
Initiates conversion “n”. Databus remains
in Hi-Z state.
0
↓
1
Initiates conversion “n”. Databus enters Hi-Z
state.
0
1
↑
Conversion “n” completed. Valid data from
conversion “n” on the databus.
↓
1
1
Enables databus with valid data from
conversion “n”.
↓
1
0
Enables databus with valid data from
conversion “n-1”
(1)
. Conversion n in process.
0
↑
0
Enables databus with valid data from
conversion “n-1”
(1)
. Conversion “n” in process.
0
0
↑
New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
X
X
0
New convert commands ignored. Conversion
“n” in process.
NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion “n-1”.
Table I. Control Line Functions for “Read” and “Convert”.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7820
0 to +5V
+5V
0.1μF
10μF
+
+
2.2μF
+
+
2.2μF
Convert Pulse
40ns min
5.4μs max
B0 (LSB)
B1
B2
B3
LOW
LOW
LOW
LOW
B6
B5
B4
B7
B8
B9
B10
B11 (MSB)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7820U | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| ADS7821 | 制造商:BB 制造商全稱:BB 功能描述:16-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7821P | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADS7821PB | 制造商:BB 制造商全稱:BB 功能描述:16-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
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