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參數(shù)資料
| 型號： | ADS7817 |
| 英文描述： | 12-Bit Differential Input Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 12位差分輸入微功耗采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 172K |
| 代理商： | ADS7817 |
10
ADS7817
CS/SHDN
D
OUT
DCLOCK
t
DATA
t
SUCS
t
CYC
t
CONV
POWER
DOWN
t
SMPL
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output LSB-First data then followed with zeroes indefinitely.
B11
(MSB)
B10 B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
(1)
NULL
BIT
HI-Z
HI-Z
B11 B10
B9
B8
NULL
BIT
CS/SHDN
D
OUT
DCLOCK
t
CONV
t
DATA
t
SUCS
t
CSD
HI-Z
t
CSD
t
CYC
POWER DOWN
t
SMPL
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output zeroes indefinitely.
t
: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
B11
(MSB)
B10 B9
B8
B7
B6
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
NULL
BIT
HI-Z
B5
B6
B7
B8
B9
B10 B11
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, D
OUT
is enabled and will output a LOW
value for one clock period. For the next 12 DCLOCK
periods, D
OUT
will output the conversion result, most sig-
nificant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B11) has been repeated, D
OUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
DATA FORMAT
The output data from the ADS7817 is in Binary Two’s
Complement format as shown in Table II. This table repre-
sents the ideal output code for the given input voltage and
does not include the effects of offset, gain error, or noise.
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS7817 to
convert at up to a 200kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS7817 scales directly with
conversion rate. The first step to achieving the lowest power
dissipation is to find the lowest conversion rate that will
satisfy the requirements of the system.
In addition, the ADS7817 is in power down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably, at a 3.2MHz clock
rate. This way, the converter spends the longest possible
time in the power down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the compara-
tor. The analog section dissipates power continuously, until
the power down mode is entered.
Figure 6 shows the current consumption of the ADS7817
versus sample rate. For this graph, the converter is clocked
at 3.2MHz regardless of the sample rate—CS is HIGH for
the remaining sample period. Figure 7 also shows current
consumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
FIGURE 4. ADS7817 Basic Timing Diagrams.
DESCRIPTION
ANALOG VALUE
Full Scale Input Span
2 V
REF
Least Significant
Bit (LSB)
2 V
REF
/4096
+Full Scale
V
REF
–1 LSB
0111 1111 1111
7FF
Midscale
0V
0000 0000 0000
000
Midscale – 1 LSB
0V – 1 LSB
1111 1111 1111
FFF
–Full Scale
–V
REF
1000 0000 0000
800
TABLE II. Ideal Input Voltages and Output Codes.
DIGITAL OUTPUT:
BINARY TWO’S COMPLEMENT
BINARY CODE
HEX CODE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS7817B | 12-Bit Differential Input Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7817C | 12-Bit Differential Input Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7818 | 2SC5161 |
| ADS7818E | 2SC5161 |
| ADS7818EB | 2SC5161 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7817B | 制造商:BB 制造商全稱:BB 功能描述:12-Bit Differential Input Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7817C | 制造商:BB 制造商全稱:BB 功能描述:12-Bit Differential Input Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7817E | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-Bit Differential Input Micro Power Sampling |
| ADS7817E/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit Differential In MicroPwr Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7817E/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit Differential In MicroPwr Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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