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參數(shù)資料
| 型號： | ADS7812UG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SER 40K 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 35mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 3 個單端，單極；3 個單端，雙極 |
ADS7812
8
SBAS042A
www.ti.com
Convert
Acquire
MODE
BUSY
CONV
t
3
t
2
t
1
t
5
t
4
t
7
t
6
t
8
t
10
t
11
t
9
FIGURE 2. Basic Conversion Timing.
SYMBOL
DESCRIPTION
MIN
TYP MAX UNITS
t1
Conversion Plus Acquisition Time
25
s
t2
CONV LOW to All Digital
8
s
Inputs Stable
t3
CONV LOW to Initiate a Conversion
40
ns
t4
BUSY Rising to Any Digital
0
ns
Input Active
t5
CONV HIGH Prior to Start
2
s
of Conversion
t6
BUSY LOW
15
20
s
t7
CONV LOW to BUSY LOW
85
120
ns
t8
Aperture Delay
40
ns
t9
Conversion Time
14
20
s
t10
Conversion Complete to
1.1
2
s
BUSY Rising
t11
Acquisition Time
5
s
t12
CONV LOW to Rising Edge
1.4
s
of First DATACLK
t13
Internal DATACLK HIGH
250
350
500
ns
t14
Internal DATACLK LOW
600
760
875
ns
t15
Internal DATACLK Period
1.1
s
t16
DATA Valid to Internal
20
ns
DATACLK Rising
t17
Internal DATACLK Falling
400
ns
to DATA Not Valid
t18
Falling Edge of Last DATACLK
800
ns
to BUSY Rising
t19
External DATACLK Rising
15
ns
to DATA Not Valid
t20
External DATACLK Rising
55
85
ns
to DATA Valid
t21
External DATACLK HIGH
50
ns
t22
External DATACLK LOW
50
ns
t23
External DATACLK Period
100
ns
t24
CONV LOW to External
120
ns
DATACLK Active
t25
External DATACLK LOW
2
s
or CS HIGH to BUSY Rising
t26
CS LOW to Digital Outputs Enabled
85
ns
t27
CS HIGH to Digital Outputs Disabled
85
ns
TABLE II. ADS7812 Timing. TA = –40°C to +85°C.
STARTING A CONVERSION
If a conversion is not currently in progress, a falling edge on
the CONV input places the sample and hold into the hold
mode and begins a conversion, as shown in Figure 2 and
with the timing given in Table II. During the conversion, the
CONV input is ignored. Starting a conversion does not
depend on the state of CS. A conversion can be started once
every 25
s (40kHz maximum conversion rate). There is no
minimum conversion rate.
Even though the CONV input is ignored while a conversion
is in progress, this input should be held static during the
conversion period. Transitions on this digital input can
easily couple into sensitive analog portions of the converter,
adversely affecting the conversion results (see the Sensitiv-
ity to External Digital Signals section of this data sheet for
more information).
Ideally, the CONV input should go LOW and remain LOW
throughout the conversion. It should return HIGH sometime
after BUSY goes HIGH. In addition, it should be HIGH
prior to the start of the next conversion for a minimum time
period given by t5. This will ensure that the digital transition
on the CONV input will not affect the signal that is acquired
for the next conversion.
An acceptable alternative is to return the CONV input HIGH
as soon as possible after the start of the conversion. For
example, a negative going pulse 100ns wide would make a
good CONV input signal. It is strongly recommended that
from time t2 after the start of a conversion until BUSY rises,
the CONV input should be held static (either HIGH or
LOW). During this time, the converter is more sensitive to
external noise.
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| ADS7813 | 制造商:BB 制造商全稱:BB 功能描述:Low-Power, Serial 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
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