參數(shù)資料
型號: ADS7812UB
廠商: Texas Instruments
文件頁數(shù): 6/24頁
文件大?。?/td> 0K
描述: IC 12BIT 35MW SER OUT A/D 16SOIC
產(chǎn)品培訓模塊: Data Converter Basics
標準包裝: 40
位數(shù): 12
采樣率(每秒): 40k
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 35mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 16-SOIC
包裝: 管件
輸入數(shù)目和類型: 3 個單端,單極;3 個單端,雙極
ADS7812
14
SBAS042A
www.ti.com
The range for the external reference is 2.3V to 2.7V. The
voltage on REF determines the full-scale range of the con-
verter and the corresponding LSB size. Increasing the refer-
ence voltage will increase the LSB size in relation to the
internal noise sources which, in turn, can improve signal-to-
noise ratio. Likewise, decreasing the reference voltage will
reduce the LSB size and signal-to-noise ratio.
CAP
The CAP pin is used to compensate the internal reference
buffer. A 1
F tantalum capacitor in parallel with a 0.01F
ceramic capacitor should be connected between this pin and
ground, with the ceramic capacitor placed as close as pos-
sible to the ADS7812. The total value of the capacitance on
the CAP pin is critical to optimum performance of the
ADS7812. A value larger than 2.0
F could overcompensate
the buffer while a value lower than 0.5
F may not provide
adequate compensation.
BUF
The voltage on the BUF pin is the output of the internal
reference buffer. This pin is used to provide +2.5V to the
analog input or inputs for the various input configurations.
The BUF output can provide up to 1mA of current to an
external load. The load should be constant as a variable load
could affect the conversion result by modulating the BUF
voltage. Also note that the BUF output will show significant
glitches as each bit decision is made during a conversion.
Between conversions, the BUF output is quiet.
POWER DOWN
The ADS7812 has a power-down mode that is activated by
taking CONV LOW and then PWRD HIGH. This will
power down all of the analog circuitry including the refer-
ence, reducing power dissipation to under 50
W. To exit the
power-down mode, CONV is taken HIGH and then PWRD
is taken LOW. Note that a conversion will be initiated if
PWRD is taken HIGH while CONV is LOW.
While in the power-down mode, the voltage on the capaci-
tors connected to CAP and REF will begin to leak off. The
voltage on the CAP capacitor leaks off much more rapidly
than the REF capacitor (the REF input of the ADS7812
becomes high impedance when PWDN is HIGH—this is not
true for the CAP input). When the power-down mode is
exited, these capacitors must be allowed to recharge and
settle to a 12-bit level. Figure 11 shows the amount of time
typically required to obtain a valid 12-bit result based on the
amount of time spent in power down (at room temperature).
This figure assumes that the total capacitance on the CAP
pin is 1.01
F.
Figure 12 provides a circuit which can significantly reduce
the power up time if the power down time will be fairly brief
(a few seconds or less). A low on-resistance MOSFET is
used to disconnect the capacitance on the CAP pin from the
leakage paths internal to the ADS7812. This allows the
capacitors to retain their charge for a much longer period of
time, reducing the time required to recharge them at power
up. With this circuit, the power down time can be extended
to tens or hundreds of milliseconds with almost instanta-
neous power up.
FIGURE 12. Improved Power-Up Response Circuit.
FIGURE 11. Power-Down to Power-Up Response.
POWER-DOWN TO POWER-UP RESPONSE
Power-Down Duration (ms)
Power-Up
Time
to
Rated
Accuracy
(s)
300
250
200
150
100
50
0
0.1
1
10
100
T
A = +25°C
V
S
PWRD
BUSY
CS
CONV
EXT/INT
DATA
DATACLK
R1
IN
GND
R2
IN
R3
IN
BUF
CAP
REF
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
8
7
6
5
0.01F
1F
1RF7604
+
Power-Down Signal
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