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參數資料
| 型號： | ADS7812P |
| 廠商： | Texas Instruments |
| 文件頁數： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LP SERIAL 12-BIT A/D 16-DIP |
| 產品培訓模塊： | Data Converter Basics |
| 標準包裝： | 25 |
| 位數： | 12 |
| 采樣率（每秒）： | 40k |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 35mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 16-PDIP |
| 包裝： | 管件 |
| 輸入數目和類型： | 3 個單端，單極；3 個單端，雙極 |
| 產品目錄頁面： | 891 (CN2011-ZH PDF) |
ADS7812
11
SBAS042A
www.ti.com
might be possible to use the rising edge of the DATACLK
signal. However, one extra clock period (not shown in
Figures 6, 7, and 8) is needed for the final bit.
The external DATACLK signal must be LOW or CS must
be HIGH prior to BUSY rising (see time t25 in Figures 7 and
8). If this is not observed, the output shift register of the
ADS7812 will not be updated with the conversion result.
Instead, the previous contents of the shift register will
remain and the new result will be lost.
If more than 12 clock cycles are provided to the DATACLK
input, the DATA output will go LOW after the rising edge
of the 13th clock period. The operation of the ADS7812 will
not be affected as long as the timing specifications are met.
Before reading the next three paragraphs, consult the Sensi-
tivity to External Digital Signals section of this data sheet.
This will explain many of the concerns regarding how and
when to apply the external DATACLK signal.
External DATACLK Active After the Conversion
The preferred method of obtaining the conversion result is to
provide the DATACLK signal after the conversion has been
completed and before the next conversion starts—as shown
in Figure 6. Note that the DATACLK signal should be static
before the start of the next conversion. If this is not ob-
served, the DATACLK signal could affect the voltage that
is acquired.
External DATACLK Active During the Next Conversion
Another method of obtaining the conversion result is shown
in Figure 7. Since the output shift register is not updated until
the end of the conversion, the previous result remains valid
during the next conversion. If a fast clock (
≥ 2MHz) can be
provided to the ADS7812, the result can be read during time
t2. During this time, the noise from the DATACLK signal is
less likely to affect the conversion result.
FIGURE 7. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/INT HIGH,
CS LOW).
FIGURE 8. Serial Data Timing, External Clock, Clocking After the Conversion Completes and During the Next Conversion
(EXT/INT HIGH, CS LOW).
BUSY
CONV
t
24
t
4
t
5
DATACLK
t
25
1
2
n
n+1
11
12
DATA
MSB
Bit 10
Bit n
Bit n-1
Bit 1
LSB
34
BUSY
CONV
t
2
t
1
DATACLK
t
24
t
25
t
23
t
22
t
21
t
20
t
19
1
211
12
DATA
MSB
Bit 10
Bit 9
Bit 1
LSB
MSB
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADS7812P | 制造商:Texas Instruments 功能描述:IC 12BIT ADC SERIAL PDIP16 7812 |
| ADS7812PB | 功能描述:模數轉換器 - ADC Low-Power Serial 12-Bit Sampling RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7812PBG4 | 功能描述:模數轉換器 - ADC Low-Power Serial 12-Bit Sampling RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7812PG4 | 功能描述:模數轉換器 - ADC Low-Power Serial 12-Bit Sampling RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7812U | 功能描述:模數轉換器 - ADC Low-Power Serial 12-Bit Sampling RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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