參數(shù)資料
型號: ADS7807P
英文描述: CMOS Quad 2-Input NOR Gate 14-SOIC -55 to 125
中文描述: 低功耗16位采樣CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 13/23頁
文件大小: 524K
代理商: ADS7807P
ADS7807
SBAS022B
13
www.ti.com
used for each input range (see Figure 8). The input resistor
divider network provides inherent over-voltage protection to
at least
±
5.5V for R2
IN
and
±
12V for R1
IN
.
Analog inputs above or below the expected range will yield
either positive full-scale or negative full-scale digital outputs,
respectively. Wrapping or folding over for analog inputs
outside the nominal range will not occur.
CALIBRATION
HARDWARE CALIBRATION
To calibrate the offset and gain of the ADS7807 in hardware,
install the resistors shown in Figure 7a. Table VI lists the
hardware trim ranges relative to the input for each input
range.
SOFTWARE CALIBRATION
To calibrate the offset and gain in software, no external
resistors are required. However, to get the data sheet speci-
fications for offset and gain, the resistors shown in Figure 7b
OFFSET ADJUST
RANGE (mV)
GAIN ADJUST
RANGE (mV)
INPUT RANGE
±
10V
±
15
±
60
0 to 5V
±
4
±
30
0 to 4V
±
3
±
30
TABLE VI. Offset and Gain Adjust Ranges for Hardware
Calibration (see Figure 7a).
FIGURE 7b. Circuit Diagrams (Without Hardware Trim).
are necessary. See the No Calibration section for more
details on the external resistors. Refer to Table VIII for the
range of offset and gain errors with and without the external
resistors.
NO CALIBRATION
Figure 7b shows circuit connections. Note that the actual
voltage dropped across the external resistors is at least two
orders of magnitude lower than the voltage dropped across
the internal resistor divider network. This should be consid-
±
10V
0V-5V
0V-4V
FIGURE 7a. Circuit Diagrams (With Hardware Trim).
±
10V
0V-5V
0V-4V
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
1M
+5V
50k
+5V
100
33.2k
50k
V
IN
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
1M
+5V
50k
50k
33.2k
100
V
IN
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
33.2k
100
V
IN
1M
+5V
50k
50k
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
100
+5V
66.5k
V
IN
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
33.2k
100
V
IN
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
33.2k
100
V
IN
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