參數資料
型號: ADS7806
英文描述: CMOS Quad 2-Input NOR Gate 14-SOIC -55 to 125
中文描述: 低功耗12位采樣CMOS模擬數字轉換器
文件頁數: 13/18頁
文件大小: 209K
代理商: ADS7806
13
ADS7806
OFFSET ADJUST
RANGE (mV)
GAIN ADJUST
RANGE (mV)
INPUT RANGE
±
10V
±
15
±
60
0 to 5V
±
4
±
30
0 to 4V
±
3
±
30
TABLE VII. Offset and Gain Adjust Ranges for Hardware
Calibration (see Figure 7a).
±
10V
0-5V
0-4V
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
100
+5V
66.5k
V
IN
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
33.2k
100
V
IN
FIGURE 7b. Circuit Diagrams (Without Hardware Trim).
±
10V
0-5V
0-4V
FIGURE 7a. Circuit Diagrams (With Hardware Trim).
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
33.2k
100
V
IN
1M
+5V
50k
50k
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
1M
+5V
50k
50k
33.2k
100
V
IN
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
1M
+5V
50k
+5V
100
33.2k
50k
V
IN
used for each input range (see Figure 8). The input resistor
divider network provides inherent overvoltage protection
guaranteed to at least
±
25V.
Analog inputs above or below the expected range will yield
either positive full scale or negative full scale digital outputs
respectively. There will be no wrapping or folding over for
analog inputs outside the nominal range.
CALIBRATION
HARDWARE CALIBRATION
To calibrate the offset and gain of the ADS7806 in hard-
ware, install the resistors shown in Figure 7a. Table VII lists
the hardware trim ranges relative to the input for each input
range.
SOFTWARE CALIBRATION
To calibrate the offset and gain in software, no external
resistors are required. However, to get the data sheet speci-
fications for offset and gain, the resistors shown in Figure 7b
are necessary. See the
No Calibration
section for more
details on the external resistors. Refer to Table VIII for the
range of offset and gain errors with and without the external
resistors.
NO CALIBRATION
See Figure 7b for circuit connections. Note that the actual
voltage dropped across the external resistors is at least two
orders of magnitude lower than the voltage dropped across
the internal resistor divider network. This should be consid-
200
1
2
3
4
5
6
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
+
+
2.2μF
2.2μF
33.2k
100
V
IN
相關PDF資料
PDF描述
ADS7806P CMOS Quad 2-Input NOR Gate 14-SOIC -55 to 125
ADS7806PB Low-Power 12-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7806U Low-Power 12-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7806UB Low-Power 12-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER
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