參數(shù)資料
型號(hào): ADS7805UB
英文描述: 16-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER
中文描述: 16位10ms的采樣CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 8/12頁(yè)
文件大小: 135K
代理商: ADS7805UB
8
ADS7805
READING DATA
The ADS7805 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS
(pin 25) is LOW. Any other combination of CS and R/C will
tri-state the parallel output. Valid conversion data can be
read in a full parallel, 16-bit word or two 8-bit bytes on pins
6-13 and pins 15-22. BYTE (pin 23) can be toggled to read
both bytes within one conversion cycle. Refer to Table III
for ideal output codes and Figure 2 for bit locations relative
to the state of BYTE.
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 7
μ
s after
the start of conversion ‘n’. Do not attempt to read data from
7
μ
s after the start of conversion ‘n’ until BUSY (pin 26)
goes HIGH; this may result in reading invalid data. Refer to
Table IV and Figures 3 and 5 for timing specifications.
Note!
For the best possible performance, data should not be
read during a conversion. The switching noise of the asyn-
chronous data transfer can cause digital feedthrough degrad-
ing the converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 3.
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
DESCRIPTION
ANALOG INPUT
BINARY CODE
HEX CODE
Full Scale Range
±
10V
Least Significant
Bit (LSB)
305
μ
V
+Full Scale
(10V – 1LSB)
9.999695V
0111 1111 1111 1111
7FFF
Midscale
0V
0000 0000 0000 0000
0000
One LSB below
Midscale
–305
μ
V
1111 1111 1111 1111
FFFF
–Full Scale
–10V
1000 0000 0000 0000
8000
Table III. Ideal Input Voltages and Output Codes.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D15-D0 (pin 6-13
and 15-22). BUSY going HIGH can be used to latch the
data. Refer to Table IV and Figures 3 and 5 for timing
specifications.
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
t
1
Convert Pulse Width
40
7000
ns
t
2
Data Valid Delay after R/C LOW
8
μ
s
t
3
t
4
BUSY Delay from R/C LOW
BUSY LOW
65
8
ns
μ
s
t
5
BUSY Delay after
End of Conversion
220
ns
t
6
Aperture Delay
40
ns
t
7
Conversion Time
7.6
8
μ
s
t
8
Acquisition Time
2
μ
s
t
9
Bus Relinquish Time
10
35
83
ns
t
10
BUSY Delay after Data Valid
50
200
ns
t
11
Previous Data Valid
after R/C LOW
7.4
μ
s
t
7
+ t
6
Throughput Time
9
10
μ
s
t
12
t
13
t
14
R/C to CS Setup Time
10
ns
Time Between Conversions
10
μ
s
Bus Access Time
and BYTE Delay
10
83
ns
TABLE IV. Conversion Timing.
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 15 (MSB)
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS7805
BYTE LOW
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15 (MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS7805
BYTE HIGH
+5V
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