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參數(shù)資料
| 型號(hào)： | ADS7803 |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 3W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting |
| 中文描述： | Autocalibrating，4通道，12位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 99K |
| 代理商： | ADS7803 |
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ADS7803
8
LOW, the output data will change to correspond to the HBE
input. Figure 4 shows the timing for reading first the Low
byte and then the High byte.
ADS7803 provides two modes for reading the conversion
results. At power-up, the converter is set in the Transparent
Mode.
TRANSPARENT MODE
This is the default mode for ADS7803. In this mode, the
conversion decisions from the successive approximation
register are latched into the output register as they are made.
Thus, the High byte (the 4 MSBs) can be read after the end
of the ninth clock cycle (five clock cycles for the mux
settling, sample acquisition and auto-zeroing of the com-
parator, followed by the four clock cycles for the 4MSB
decisions.) The complete 12-bit data is available after BUSY
has gone HIGH, or the internal status flag goes LOW (D7
when HBE is HIGH).
LATCHED OUTPUT MODE
This mode is activated by writing a HIGH to D0 in the
Special Function Register with CS and WR LOW and SFR
and HBE HIGH. (See the discussion of the Special Function
Register below.)
In this mode, the data from a conversion is latched into the
output buffers only after a conversion is complete, and
remains there until the next conversion is completed. The
conversion result is valid during the next conversion. This
allows the data to be read even after a new conversion is
started, for faster system throughput.
SYMBOL
PARAMETER
(1)
MIN
TYP
MAX
UNITS
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
CS to WR Setup Time
(2)
WR or CAL Pulse Width
CS to WR Hold Time
(2)
WR to BUSY Propagation Delay
A0, A1, HBE, SFR Valid to WR Setup Time
A0, A1, HBE, SFR Valid to WR Hold Time
BUSY to CS Setup Time
CS to RD Setup Time
(2)
RD Pulse Width
CS to RD Hold Time
(2)
HBE, SFR to RD Setup Time
HBE, SFR to RD Hold Time
RD to Valid Data (Bus Access Time)
(3)
RD to Hi-Z Delay (Bus Release Time)
(3)
RD to Hi-Z Delay For SFR
(3)
Data Valid to WR Setup Time
Data Valid to WR Hold Time
Acquisition Time. Pin 26 LOW with D2 in SFR HIGH
Sample-to-Hold Aperture Delay. (D2 in SFR HIGH)
Delay from rising edge on pin 26 to start of conversion.
(D2 in SFR HIGH)
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
ns
100
0
20
0
20
0
0
100
0
50
0
0
50
0
150
0
0
0
0
80
90
150
180
60
20
100
20
2.5
5
1.5
CLK cycles
NOTES: (1) All input control signals are specified with t
= t
= 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Data is timed from V
IH
,
V
, V
or V
. (2) The internal RD pulse is performed by a NOR wiring of CS and RD. The internal WR pulse is performed by a NOR wiring of CS and WR.
(3) Figures 8 and 9 show the measurement circuits and pulse diagrams for testing transitions to and from Hi-Z states.
TABLE I. Timing Specifications (CLK = 2MHz external, T
A
= –40
°
C to +85
°
C).
TIMING CONSIDERATIONS
Table I and Figures 3 through 9 show the digital timing of
ADS7803 under the various operating modes. All of the
critical parameters are guaranteed over the full –40
°
C to
+85
°
C operating range for ease of system design.
SPECIAL FUNCTION REGISTER (SFR)
An internal register is available, either to determine addi-
tional data concerning the ADS7803, or to write additional
instructions to the converter.
Table II shows the data in the Special Function Register that
will be transferred to the output bus by driving HBE HIGH
(with SFR HIGH) and initiating a read cycle (driving RD
and CS LOW with WR HIGH.) The Power Fail flag in the
SFR is set when the power supply falls below about 3V. The
flag also means that a new calibration has been started, and
any data written to the SFR has been lost. Thus, the ADS7803
will again be in the Transparent Mode. Writing a LOW to
D5 in the SFR resets the Power Fail flag. The Cal Error flag
in the SFR is set when an overflow occurs during calibra-
tion, which may happen in very noisy systems. It is reset by
starting a calibration, and remains low after a calibration
without an overflow is completed.
Table III shows how instructions can be transferred to the
Special Function Register by driving HBE HIGH (with SFR
HIGH) and initiating a write cycle (driving WR and CS
LOW with RD HIGH.) Note that writing to the SFR also
initiates a new conversion.
相關(guān)PDF資料 |
PDF描述 |
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| ADS7803BN | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7803BP | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7807UBE4 | Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7807UBG4 | Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7803BN | 制造商:BB 制造商全稱:BB 功能描述:Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7803BP | 制造商:BB 制造商全稱:BB 功能描述:Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7804 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7804P | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 10us Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7804PB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 10us Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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