參數(shù)資料
型號(hào): ADS7800KP
英文描述: Bus LVDS 2x2 Crosspoint/Repeater
中文描述: 12位為3ms采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 10/12頁(yè)
文件大?。?/td> 122K
代理商: ADS7800KP
ADS7800
10
FIGURE 7. Read Mode: R/C Pulse HIGH— Outputs Enabled Only When R/C is High.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
t
W
t
DBC
t
B
t
AP
t
AP
t
C
t
DBE
t
DB
t
A
t
A
+t
C
t
HDR
t
S
t
H
t
DD
t
HDR
t
HL
R/C Pulse Width
BUSY delay from R/C
BUSY LOW
Aperture Delay
Aperture Jitter
Conversion Time
BUSY from End of Conversion
BUSY Delay after Data Valid
Acquisition Time
Throughput Time
Valid Data Held After R/C LOW
CS or HBE LOW before R/C Falls
CS or HBE LOW after R/C Falls
40
10
80
2.5
13
150
2.47
100
75
130
2.6
50
5
0
65
50
50
ns
ns
μ
s
ns
150
2.7
ps, rms
μ
s
ns
ns
ns
μ
s
ns
ns
ns
ns
ns
ns
2.70
25
200
300
3.0
20
25
25
Data Valid from CS LOW, R/C HIGH, and HBE in Desired State (Load = 100pF)
Valid Data Held After R/C Low
Delay to Hi-Z State after R/C Falls or CS Rises (3k
Pullup or Pulldown)
150
20
150
TABLE III. Timing Specifications (T
MIN
to T
MAX
).
Pin 24 may be slightly more sensitive than pin 23 to supply
variations, but to maintain maximum system accuracy, both
should be well isolated from digital supplies with wide load
variations.
To limit the effects of digital switching elsewhere in a
system on the analog performance of the system, it often
makes sense to run a separate +5V supply conductor from
the supply regulator to any analog components requiring
+5V, including the ADS7800.
The V
S
pins (23 and 24) should be connected together and
bypassed with a parallel combination of a 6.8
μ
F tantalum
capacitor and a 0.1
μ
F ceramic capacitor located close to the
converter to obtain noise-free operation. (See Figure 2.) The
–V
S
pin 22 should be bypassed with a 1
μ
F tantalum
capacitor, again as close as possible to the ADS7800.
Noise on the power supply lines can degrade converter
performance, especially noise and spikes from a switching
power supply. Appropriate supplies or filters must be used.
The GND pins (4 and 13) are also separated internally, and
should be directly connected to a ground plane under the
FIGURE 8. Conversion Start Timing.
R/C
Converter
Mode
BUSY
Acquire
Convert
Acquire
Convert
Data
Valid
Hi-Z State
Data
BUS
Hi-Z State
Hi-Z State
Data
Valid
t
HDR
and t
HL
t
C
t
AP
t
DBE
t
DD
t
DBC
t
W
t
B
t
A
t
AP
CS or
HBE
R/C
BUSY
t
S
t
H
t
W
t
DBC
Data
Bus
Hi-Z State
Data Valid
t
HDR
and t
HL
相關(guān)PDF資料
PDF描述
ADS7800AH 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER
ADS7800BH 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER
ADS7800JP 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER
ADS7800JU 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER
ADS7800KU 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER
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