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參數(shù)資料
| 型號： | ADS7616A4A-55 |
| 廠商： | ADATA Technology Co., Ltd. |
| 英文描述： | Synchronous DRAM(2M X 16 Bit X 4 Banks) |
| 中文描述： | 同步DRAM（2米× 16位× 4個銀行） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 565K |
| 代理商： | ADS7616A4A-55 |
A-Data
ADS7616A4A
Pin Description
PIN
NAME
FUNCTION
CLK
System Clock
Active on the positive edge to sample all inputs.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CLK, CKE and L(U)DQM
A0~A11
Address
Row / Column address are multiplexed on the same pins.
Row address : RA0~RA11
Column address : CA0~CA8
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ15 Data
Data inputs / outputs are multiplexed on the same pins.
L(U)DQM Data Mask
Makes data output Hi-Z,
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
/CAS
Column Address Strobe
Latches Column addresses on the positive edge of the CLK with /CAS low
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for output buffers.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
CKE
Clock
Generator
Address
/CS
/RAS
/CAS
/WE
L(U)DQM
Mode
Register
C
C
R
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank0
Bank2
Bank1
Bank3
Amplifier
Column Decoder
Data Control Circuit
D
DQ
Rev 1.0 April, 2001
2
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