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參數(shù)資料
| 型號(hào)： | ADS7608A4A |
| 廠商： | ADATA Technology Co., Ltd. |
| 英文描述： | Synchronous DRAM(4M X 8 Bit X 4 Banks) |
| 中文描述： | 同步DRAM（4米× 8位× 4銀行） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 696K |
| 代理商： | ADS7608A4A |
A-Data
ADS7608A4A
AC Characteristics
-5
-5.5
-6
-7
-7.5
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min Max
Unit Note
/CAS Latency = 3 tCK3
5
5.5
6
7
7.5
System clock
Cycle time
/CAS Latency = 2 tCK2
10
1000
10
1000
10
1000
10
1000
7.5
1000 ns
Clock high pulse width
tCHW
2
-
2.25
-
2.5
-
2.5
-
2.5
-
ns
1
Clock low pulse width
tCLW
2
-
2.25
-
2.5
-
2.5
-
2.5
-
ns
1
/CAS Latency = 3 tAC3
-
4.5
-
5
-
5.4
-
5.4
-
5.4
Access time
form clock
/CAS Latency = 2 tAC2
-
6
-
6
-
6
-
6
-
5.4
ns
2
Operation
tRC
55
-
55
-
60
-
62
-
65
-
/RAS cycle
time
Auto Refresh
tRRC
55
-
55
-
60
-
62
-
65
-
ns
/RAS to /CAS delay
tRCD
15
-
16.5
-
18
-
20
-
15
-
ns
/RAS active time
tRAS
40
100K 38.5 100K
42
100K
42
120K 45 120K ns
/RAS precharge time
tRP
15
-
16.5
-
18
-
20
-
15
-
ns
/RAS to /RAS bank active delay
tRRD
10
-
11
-
12
-
14
-
15
-
ns
/CAS to /CAS delay
tCCD
1
-
1
-
1
-
1
-
1
-
CLK
Write command to data – in delay tWTL
0
-
0
-
0
-
0
-
0
-
CLK
Data – in to precharge command
tDPL
1
-
1
-
1
-
1
-
1
-
CLK
Data – in active command
tDAL
5
-
5
-
5
-
4
-
4
-
CLK
DQM to data – out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
CLK
DQM to data – in mask
tDQM
0
-
0
-
0
-
0
-
0
-
CLK
Data – out hold time
tOH
1.5
-
2
-
2.7
-
2.7
-
2.7
-
ns
Data – input setup time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Data – input hold time
tDH
1
-
1
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Address hold time
tAH
1
-
1
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
CKE hold time
tCKH
1
-
1
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Command hold time
tCH
1
-
1
-
1
-
1
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1
-
1.5
-
1.5
-
ns
MRS to new command
tMRD
2
-
2
-
2
-
1
-
1
-
CLK
Power down exit time
tPDE
1
-
1
-
1
-
1
-
1
-
CLK
Self refresh exit time
tSRE
1
-
1
-
1
-
1
-
1
-
CLK
3
Refresh time
tREF
64
-
64
-
64
-
64
-
64
-
ms
Note :
1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1 April, 2001
6
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| ADS7608A4A-5 | Synchronous DRAM(4M X 8 Bit X 4 Banks) |
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| ADS7608A4A-5 | 制造商:A-DATA 制造商全稱:A-DATA 功能描述:Synchronous DRAM(4M X 8 Bit X 4 Banks) |
| ADS7608A4A-55 | 制造商:A-DATA 制造商全稱:A-DATA 功能描述:Synchronous DRAM(4M X 8 Bit X 4 Banks) |
| ADS7608A4A-6 | 制造商:A-DATA 制造商全稱:A-DATA 功能描述:Synchronous DRAM(4M X 8 Bit X 4 Banks) |
| ADS7608A4A-7 | 制造商:A-DATA 制造商全稱:A-DATA 功能描述:Synchronous DRAM(4M X 8 Bit X 4 Banks) |
| ADS7608A4A-75 | 制造商:A-DATA 制造商全稱:A-DATA 功能描述:Synchronous DRAM(4M X 8 Bit X 4 Banks) |
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