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參數(shù)資料
| 型號(hào)： | ADS574KU |
| 英文描述： | Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 微處理器兼容采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 413K |
| 代理商： | ADS574KU |
9
ADS574
FIGURE 3. R/C Pulse Low—Outputs Enabled After Conver-
sion.
FIGURE 4. R/C Pulse High — Outputs Enabled Only While
R/C Is High.
S/H CONTROL MODE
AND ADC574 EMULATION MODE
The basic difference between these two modes is the
assumptions about the state of the input signal both before
and during the conversion. The differences are shown in
Figure 9 and Table VI. In the Control Mode it is assumed
that during the required 4
μ
s acquisition time the signal is not
slewing faster than the slew rate of the ADS574. No
assumption is made about the input level after the convert
command arrives, since the input signal is sampled and
conversion begins immediately after the convert command.
This means that a convert command can also be used to
switch an input multiplexer or change gains on a program-
mable gain amplifier, allowing the input signal to settle
before the next acquisition at the end of the conversion.
Because aperture jitter is minimized by the internal sample/
hold circuit, a high input frequency can be converted without
an external sample/hold.
In the Emulation Mode, no assumption is made about the
input signal prior to the convert command. A delay time is
introduced between the convert command and the start of
conversion to allow the ADS574 enough time to acquire the
input signal before converting. The delay increases the
effective aperture time from 0.02
μ
s to 4
μ
s, but allows the
ADS574 to replace the ADC574 in any circuit. Any slewing
of the analog input prior to the convert command in existing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Convert Mode
t
DSC
t
HEC
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
STS delay from CE
CE Pulse width
CS to CE setup
CS low during CE high
R/C to CE setup
R/C low during CE high
A
O
to CE setup
A
O
valid during CE high
60
30
20
20
0
20
200
ns
ns
ns
ns
ns
ns
ns
ns
50
50
50
50
50
0
50
20
Read Mode
t
DD
t
HD
t
HL
t
SSR
t
SRR
t
SAR
t
HSR
t
HRR
t
HAR
t
HS
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
A
O
to CE setup
CS valid after CE low
R/C high after CE low
A
valid after CE low
STC delay after data valid
75
35
100
0
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
150
50
0
50
0
0
50
300
25
400
1000
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
t
HRL
t
DS
t
HDR
t
HRH
t
DDR
Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low
High R/C Pulse Width
Data Access Time
25
ns
ns
ns
ns
ns
200
25
100
150
TABLE IV. Stand-Alone Mode Timing. (T
A
= T
MIN
to T
MAX
).
TABLE V. Timing Specifications, Fully Controlled Operation. (T
A
= T
MIN
to T
MAX
).
R/C
DB11-DB0
Status
Data Valid
Data Valid
High-Z-State
t
HRL
t
DS
t
C
t
HDR
t
HS
R/C
DB11-DB0
Status
Data Valid
High-Z-State
t
HRH
t
DS
t
C
t
DDR
High-Z
t
HDR
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