參數(shù)資料
型號(hào)： ADS5542
英文描述： 14-Bit, 80MSPS Analog-to-Digital Converter
中文描述： 14位，80Msps模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 6/30頁(yè)
文件大?。?/td> 401K
代理商： ADS5542
SBAS308A MAY 2004 REVISED MARCH 2005
www.ti.com
6
TIMING CHARACTERISTICS
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
16.5 Clock Cycles
Input Clock
Output Clock
Data Out
(D0D13)
Analog
Input
Signal
Sample
N
N + 1
N + 2
N + 3
N + 4
N + 14
N + 16
N + 17
t
A
t
HOLD
Data Invalid
N + 15
t
START
t
SETUP
tPDI = tSTART + t SETUP
N 17
N 16
N 15
N 14
N 13
N 3
N 2
N 1
N
tEND
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
(1)(2)
Typical values at T
A
= +25
°
C, full temperature range is T
MIN
= 40
°
C to t
MAX
= +85
°
C, sampling rate = 80MSPS, 50% clock duty cycle, AV
DD
=
DRV
DD
= 3.3V, and 3V
PP
differential clock, unless otherwise noted.
(2)
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
Aperture delay, t
A
Aperture jitter (uncertainty)
Data setup time, t
SETUP
Data hold time, t
HOLD
Input clock to output data valid
start, t
START(4)
Input clock to output data valid end,
t
END(4)
Data rise time, t
RISE
Data fall time, t
FALL
Output enable (OE) to data output
delay
(1)Timing parameters are ensured by design and characterization, and not tested in production.
(2)See Table 5 in the
Application Information
section for timing information at additional sampling frequencies.
(3)Data valid refers to 2.0V for LOGIC HIGH and 0.8V for LOGIC LOW.
(4)Refer to the
Output Information
section for details on using the input clock for data capture.
(5)Data outputs are available within a clock from assertion of OE; however it takes 1000 clock cycles to ensure stable timing with respect to input
clock.
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
Data valid
(3)
to 50% of CLKOUT rising edge
50% of CLKOUT rising edge to data becoming invalid
(3)
1
ns
fs
ns
ns
300
4.2
3
3.2
1.8
Input clock to Data valid start delay
3.8
5
ns
Input clock to Data valid end delay
8.4
11
ns
Data rise time measured from 20% to 80% of DRV
DD
Data fall time measured from 80% to 20% of DRV
DD
Time required for outputs to have stable timings with regard to Input
Clock
(5)
after OE is activated
5.6
4.4
6.1
5.1
ns
ns
1000
Clock
Cycles
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