參數(shù)資料
型號： ADS5510IPAP
英文描述： 11-Bit, 125-MSPS Analog-To-Digital Converter
中文描述： 11位，125 MSPS的模擬到數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 6/29頁
文件大?。?/td> 835K
代理商： ADS5510IPAP
www.ti.com
TIMING CHARACTERISTICS
(1)(2)
Typical values given at T
A
= 25
°
C, min and max specified over the full recommended operating temperature range, AV
DD
=
DRV
= 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, 3-V
PP
differential clock, and C
LOAD
= 10 pF, unless
otherwise noted
ADS5510
SLAS499–JANUARY 2007
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
t
A
Aperture delay
Aperture jitter (uncertainty)
t
SETUP
Data setup time
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
Data valid
(3)
to 50% of CLKOUT rising edge
50% of CLKOUT rising edge to data becoming
invalid
(3)
1
ns
fs
ns
ns
300
2.7
2.3
1.7
2
t
HOLD
Data hold time
Input clock to output data
valid start
(4)(5)
Input clock to output data
valid end
(4)(5)
Output clock jitter
Output clock rise time
Output clock fall time
Input clock to output clock
delay
Data rise time
t
START
Input clock rising edge to data valid start delay
2
2.6
ns
t
END
Input clock rising edge to data valid end delay
5.8
6.9
ns
t
JIT
t
r
t
f
t
PDI
Uncertainty in CLKOUT rising edge, peak-to-peak
Rise time of CLKOUT from 20% to 80% of DRV
DD
Fall time of CLKOUT from 80% to 20% of DRV
DD
Input clock rising edge, zero crossing, to output
clock rising edge 50%
Data rise time measured from 20% to 80% of
DRV
DD
Data fall time measured from 80% to 20% of
DRV
DD
Time required for outputs to have stable timings
with regard to input clock
(6)
after OE is activated
Time to valid data after coming out of software
power down
Time to valid data after stopping and restarting the
clock
150
1.7
1.5
4.8
210
1.9
1.7
5.5
ps
PP
ns
ns
ns
4.2
t
r
3.6
4.6
ns
t
f
Data fall time
2.8
3.7
ns
Output enable(OE) to data
output delay
1000
Clock
cycles
1000
Clock
cycles
Wakeup time
1000
Clock
cycles
Latency
Time for a sample to propagate to the ADC outputs
17.5
(1)
(2)
(3)
(4)
(5)
Timing parameters are ensured by design and characterization, and not tested in production.
See
Table 5
through
Table 8
in the
Application Information
section for timing information at additional sampling frequencies.
Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.
See the
Output Information
section for details on using the input clock for data capture.
These specifications apply when the CLKOUT polarity is set to rising edge (according to
Table 2
). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
(6)
6
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PDF描述
ADS5510IPAPR 11-Bit, 125-MSPS Analog-To-Digital Converter
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