參數(shù)資料
型號(hào): ADS5270
英文描述: 8-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
中文描述: 8通道,12位,40MSPS的ADC的串行LVDS接口
文件頁(yè)數(shù): 5/18頁(yè)
文件大小: 439K
代理商: ADS5270
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SBAS293D JANUARY 2004 REVISED MAY 2004
www.ti.com
5
SWITCHING CHARACTERISTICS
TMIN = 40
°
C, TMAX = +85
°
C. Typical values are at TA = 25
°
C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, 1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5270
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING SPECIFICATIONS
t
SAMPLE
Aperture Delay
Aperture Jitter (uncertainty)
Latency
Propagation Delay
25
50
ns
ns
ps
t
D
(A)
2.5
1
6.5
5
t
D
(pipeline)
t
PROP
cycles
ns
SERIAL INTERFACE TIMING
Data is shifted in MSB first.
PARAMETER
t1
t2
t3
t4
t5
DESCRIPTION
Serial CLK Period
Serial CLK High Time
Serial CLK Low Time
Minimum Data Setup Time
Minimum Data Hold Time
MIN
50
TYP
MAX
UNIT
ns
ns
ns
ns
ns
25
25
5
5
Start Sequence
t
1
MSB
D6
D5
D4
D3
D2
D1
D0
t
2
t
3
t
4
t
5
ADCLK
CS
SCLK
SDATA
Outputs change on
next rising clock edge
after CS goes high.
Data latched on
each rising edge of SCLK.
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