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參數(shù)資料
| 型號： | ADS5240IPAP |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface |
| 中文描述： | 4通道，12位，40MSPS的ADC的串行LVDS接口 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 418K |
| 代理商： | ADS5240IPAP |
www.ti.com
LVDS BUFFERS
The LVDS buffer has two current sources, as shown
in Figure 17. OUT
P
and OUT
N
are loaded externally
by a resistive load that is ideally about 100
.
Depending on the data being 0 or 1, the currents are
directed in one or the other direction through the
resistor. While the lower side current source is a
constant current source, the higher side current
source is controlled through a feedback loop to
maintain the output common mode constant. The
LVDS buffer has four current settings. The default
current setting is 3.5mA, and gives a differential drop
of about
±
350mV across the 100
resistor.
NOISE COUPLING ISSUES
High-speed mixed signals are sensitive to various
types of noise coupling. One of the main sources of
noise is the switching noise from the serializer and
the output buffers. Maximum care is taken to isolate
these noise sources from the sensitive analog blocks.
As a starting point, the analog and digital domains of
the chip are clearly demarcated. AVDD and AVSS
are used to denote the supplies for the analog
sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there
is minimal interaction between the supply sets within
the
device.
The
extent
transmitted from the digital to the analog sections
depends on the following:
1. The
effective
inductances
supply/ground sets.
2. The isolation between the digital and analog
supply/ground sets.
External
Termination
Resistor
OUT
P
High
Low
OUT
N
Low
High
ADS5240
SBAS326C–JUNE 2004–REVISED DECEMBER 2004
of the clock tree for matching introduces an aperture
delay, which is defined as the delay between the
rising edge of ADCLK and the actual instant of
sampling. The aperture delays for all the channels
are matched. The aperture delays for all channels are
matched. However, across conditions of temperature,
supply voltage, and devices, the aperture delay
averages 3.1ns.
The LVDS buffer gets data from a serializer that
takes the output data from each channel and
serializes it into a single data stream. For a clock
frequency of 40MHz, the data rate output by the
serializer is 480MBPS. The data comes out LSB first,
with a register programmability to revert to MSB first.
The serializer also gives out a 1x clock and a 6x
clock. The 6x clock (denoted as LCLK
P
/LCLK
N
) is
meant to synchronize the capture of the LVDS data.
The deskew mode can be enabled as well, using a
register setting. This mode gives out a data stream of
alternate 0s and 1s and can be used determine the
relative delay between the 6x clock and the output
data for optimum capture. A 1x clock is also gener-
ated by the serializer and transmitted by the LVDS
buffer. The 1x clock (referred to as ADCLK
P
/ADCLK
N
)
is used to determine the start of the 12-bit data
frame. The sync mode (enabled through a register
setting) gives out a data of six 0s followed by six 1s.
Using this mode, the 1x clock can be used to
determine the start of the data frame. In addition to
the deskew mode pattern and the sync pattern, a
custom pattern can be defined by the user and output
from the LVDS buffer.
The input ADCLK should ideally have a 50% duty
cycle. However, while routing ADCLK to different
components on board, the duty cycle of the ADCLK
reaching the ADS5240 could deviate from 50%. A
smaller (or larger) duty cycle eats into the time
available for sample or hold phases of each circuit,
and is therefore not optimal. For this reason, the
internal PLL is used to generate an internal clock that
has 50% duty cycle.
The use of the PLL automatically dictates the mini-
mum sampling rate to be about 20MSPS.
of
noise
coupled
and
of
each
of
the
Smaller effective inductance of the supply/ground
pins leads to better suppression of the noise. For this
reason,
multiple
pins
are
supply/ground. It is also critical to ensure that the
impedances of the supply and ground lines on board
are kept to the minimum possible values. Use of
ground planes in the board as well as large decoup-
ling capacitors between the supply and ground lines
are necessary to get the best possible SNR from the
device.
used
to
drive
each
Figure 17. LVDS Buffer
19
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS5240IPAPG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Ch 12-bit 40MSPS w/Ser LVDS Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5240IPAPT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Ch 12-bit 40MSPS w/Ser LVDS Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5240IPAPTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Ch 12-bit 40MSPS w/Ser LVDS Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5242 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface |
| ADS5242EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS5242 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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