參數(shù)資料
型號(hào)： ADS5220IRGZR
英文描述： 12-Bit, 40MSPS Sampling, +3.3V ANALOG-TO-DIGITAL CONVERTER
中文描述： 12位，40MSPS采樣，3.3V的模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 13/20頁(yè)
文件大小： 433K
代理商： ADS5220IRGZR
ADS5220
SBAS261A
13
www.ti.com
remains the same for the internal or external reference
modes. The bypassing should consist of two pairs of 2.2
μ
F
ceramic and 15
μ
F tantalum capacitors, and a 10
μ
F tantalum
capacitor, as depicted in Figure 7.
In addition to the bypassing the top- and bottom reference
pin (REFT, REFB) require a pull-up and a pull-down resistor,
respectively. As shown in Figure 7, the pull-up resistor
should be connected from the REFT pin to the analog supply
(+3.3V AV
DD
), while the pull-down resistor on the REFB pin
should be connected to ground. For proper operation the
value of those resistors should be maintained as shown, that
is, 402
. Also, to ensure optimal settling of the internal
reference amplifiers the external configuration must include
two low value resistors located in series with each the REFT
and REFB pins (see Figure 7). For best results, use small
surface mount chip resistors and position them as close to
the pins as possible.
INTERNAL REFERENCE
There are two internal fixed reference modes and one
internal programmable reference mode as shown in Table I
and Figure 7 through Figure 9. Setting RSEL to ground (or
< 0.2V) provides an internal reference voltage of +1.0V at
V
REF
pin, +2V at REFT, and +1V at REFB pin. In this case,
the input FSR is +2V peak-to-peak. Connecting RSEL to the
V
REF
pin provides an internal reference voltage of +0.5V at
V
REF
, +1.75V at REFT, and +1.25V at REFB. In this case, the
input FSR is +1V peak-to-peak. Setting the resistor divider as
in Figure 9 provides an internal voltage between +0.5V and
+1V at V
REF
, which is as follows:
V
REF
= 0.5
(1+R
2
/R
1
)
In this case, the voltage at REFT and REFB and input FSR
is calculated based on Table I.
the user may prefer to disable the DCA function; for example,
during asynchronous clocking (that is, when the sampling
period is purposely not constant).
In any case, a very low jitter clock is fundamental to preserv-
ing the excellent AC performance of the ADS5220. Gener-
ally, as input frequency increases, clock jitter becomes more
critical to maintain a good signal-to-noise ratio. The following
equation can be used to calculate the achievable SNR for a
given input frequency and clock jitter (t
JA
in ps rms):
SNR
JA
= 20 log [1/(2
π
f
IN
t
JA
)]
Here, the t
JA
is the rms aperture jitter from all jitter sources,
such as clock edge, input signal and the device. The f
IN
is
input frequency. The crystal oscillator has very low jitter, but
if using a clock conditioning circuit (gate, divider, logic level
converter, and so forth), the extra jitter and timing variation
must be considered. In addition, the input clock is treated as
an analog signal and its power supply should be separated
from the power supply of the digital output driver to limit the
digital noise.
MINIMUM SAMPLING RATE
The pipeline architecture of the ADS5220 uses a switched-
capacitor technique in its internal track-and-hold stages. The
high sampling speed necessitates the use of very small
capacitor values. In order to hold droop errors low, the
capacitors require a minimum refresh rate. To maintain
accuracy of the acquired sample charge, the sampling clock
on the ADS5220 must not drop below the specified minimum
of 1MSPS.
REFERENCE
The ADS5220 provides both an internal and an external
reference mode through the configuration of pins RSEL and
V
REF
(see Table 1). The input full-scale range (FSR) of the
ADS5220 is always twice the voltage at the V
REF
pin. The
REFT and REFB pins are internally buffered, and drive the
ADC core for both the external and internal reference modes.
When the internal reference mode is selected the voltage at
V
REF
is generated by an internal 0.5V bandgap voltage
through a V
REF
amplifier.
This internal buffer amplifier can be
used to supply up to 2mA to external circuitry. Selecting the
external reference mode will power-down this reference
amplifier, and the V
REF
pin becomes the input for the external
reference voltage. In the power-down mode, the impedance
of the V
REF
pin is approximately 6k
.
Shown in Table I are the values for V
REFT
, V
REFB
, and V
REF
for the various modes and full-scale input ranges.
The ADS5220 requires its reference pins to be bypassed as
outlined in Figure 7 through Figure 10. The configuration
RSEL PIN
CONNECT TO
INPUT FSR (V
PP
)
(Differential)
SELECTED MODE
V
REF
PIN (V)
1.0
0.5
0.5
(1+R
/R
1
)
Ext. 0.5V to 1V
REFT (V)
REFB (V)
Internal Fixed
Internal Fixed
Internal Program
External
GND to 0.2V
V
Pin
0.2V to V
AV
DD
(3.3V)
2
1
2
1
1.75
1.25
2
V
REF
2
V
REF
V
REF
/2 + 1.5
V
REF
/2 + 1.5
1.5
–
V
REF
/2
1.5
–
V
REF
/2
TABLE I. Reference Configuration.
ADS5220
RSEL
VREF
REFT
REFB
2.2
μ
F
+
+
+
+
0.1
μ
F
2
10
μ
F
402
2.2
μ
F
15
μ
F
2
2.2
μ
F
15
μ
F
402
+3.3V
1V
Output
FIGURE 7. Internal Reference Mode for V
REF
= 1V.
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