參數(shù)資料
型號: ADS1254E
英文描述: 24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER
中文描述: 24位20kHz的,低功耗模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 12/17頁
文件大?。?/td> 281K
代理商: ADS1254E
ADS1254
SBAS213
12
SYMBOL
t
OSC
t
DRDY Mode
DOUT Mode
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
DESCRIPTION
CLK Period
Conversion Cycle
DRDY Mode
DOUT Mode
DOR Write Time
DOUT/DRDY LOW Time
DOUT/DRDY HIGH Time (Prior to Data Out)
DOUT/DRDY HIGH Time (Prior to Data Ready)
Rising Edge of CLK to Falling Edge of DOUT/DRDY
End of DRDY Mode to Rising Edge of First SCLK
End of DRDY Mode to Data Valid (Propagation Delay)
Falling Edge of SCLK to Data Valid (Hold Time)
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay)
SCLK Setup Time for Synchronization or Power Down
DOUT/DRDY Pulse for Synchronization or Power Down
Rising Edge of SCLK Until Start of Synchronization
Synchronization Time
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Rising Edge of SCLK Until Start of Power Down
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Falling Edge of Last DOUT/DRDY to Start of Power Down
DOUT/DRDY High Time After Mux Change.
MIN
125
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
384
t
OSC
36
t
OSC
348
t
OSC
6
t
OSC
6
t
OSC
6
t
OSC
24
t
OSC
50
30
50
5
50
30
3
t
OSC
1537
CLK
0.5
CLK
7679
CLK
6143.5
CLK
2042.5
t
OSC
7681
CLK
2318.5
t
OSC
6144.5
t
2043.5
tosc
TABLE III. Digital Timing.
SERIAL INTERFACE
The ADS1254 includes a simple serial interface that can be
connected to microcontrollers and digital signal processors
in a variety of ways. Communications with the ADS1254
can commence on the first detection of the DOUT/DRDY
pulse after power up.
It is important to note that the data from the ADS1254 is a
24-bit result transmitted MSB-first in Offset Two’s Comple-
ment format, as shown in Table IV.
The data must be clocked out before the ADS1254 enters
DRDY mode to ensure reception of valid data, as described
in the DOUT/DRDY section of this data sheet.
ISOLATION
The serial interface of the ADS1254 provides for simple
isolation methods. The CLK signal can be local to the
ADS1254, which then only requires two signals (SCLK and
DOUT/DRDY) to be used for isolated data acquisition. The
channel select signals (CHSEL0, CHSEL1) will also need to
be isolated unless a counter is used to auto multiplex the
channels.
TABLE IV. ADS1254 Data Format (Offset Two's Comple-
ment).
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
+Full Scale
Zero
Full Scale
7FFFFFH
000000H
800000H
FIGURE 13. Multiplexer Operation.
DATA
DATA
DOUT/DRDY
t
18
MUX CHANGE
CHSEL0, CHSEL1
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