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參數(shù)資料
| 型號(hào)： | ADS1252U/2K5G4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24-BIT SER 41.7KHZ 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 41.7k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 40mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | 296-19906-ND - EVAL MOD FOR ADS1252 |
ADS1252
12
SBAS127D
www.ti.com
POWER-DOWN MODE
The normal state of SCLK is LOW; however, by holding
SCLK HIGH, the ADS1252 enters power-down mode. This is
accomplished by holding SCLK HIGH for at least 20 con-
secutive DOUT/DRDY periods (see Figure 14). After the
ADS1252 circuitry detects that SCLK is held HIGH for four
consecutive DOUT/DRDY cycles, the DOUT/DRDY pin pulses
LOW for three CLK cycles, then held HIGH, and the modu-
lator will be held in a reset state. If SCLK is held HIGH for an
additional 16 DOUT/DRDY periods, the ADS1252 enters
power-down mode and the part is released from power-down
mode on the falling edge of SCLK. It is important to note that
the DOUT/DRDY pin is held HIGH after four DOUT/DRDY
cycles, but power-down mode is not entered for an additional
16 DOUT/DRDY periods. The first DOUT/DRDY pulse after
the falling edge of SCLK occurs at t16; however, subsequent
DOUT/DRDY pulses occur normally. Valid data is not present
until the sixth DOUT/DRDY pulse.
SERIAL INTERFACE
The ADS1252 includes a simple serial interface which can be
connected to microcontrollers and digital signal processors in
a variety of ways. Communications with the ADS1252 can
commence on the first detection of the DOUT/DRDY pulse
after power up, although data is valid until the sixth conver-
sion.
It is important to note that the data from the ADS1252 is a
24-bit result transmitted MSB-first in Offset Binary Two’s
Complement format, as shown in Table III.
The data must be clocked out before the ADS1252 enters
DRDY mode to ensure reception of valid data, as described
in the DOUT/DRDY section of this data sheet.
FIGURE 11. DOUT/DRDY Partitioning.
DATA
DRDY Mode
DOUT Mode
DATA
t
4
t
2
t
3
t
1
DRDY Mode
DOUT/DRDY
TABLE III. ADS1252 Data Format (Offset Binary Two's
Complement).
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
+Full-Scale
7FFFFFH
Zero
000000H
–Full-Scale
800000H
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tDRDY
Conversion Cycle
384 CLK
ns
DRDY Mode
36 CLK
ns
DOUT Mode
348 CLK
ns
t1
DOR Write Time
6 CLK
ns
t2
DOUT/DRDY LOW Time
6 CLK
ns
t3
DOUT/DRDY HIGH Time (Prior to Data Out)
6 CLK
ns
t4
DOUT/DRDY HIGH Time (Prior to Data Ready)
24 CLK
ns
t5
Rising Edge of CLK to Falling Edge of DOUT/DRDY
30
ns
t6
End of DRDY Mode to Rising Edge of First SCLK
30
ns
t7
End of DRDY Mode to Data Valid (Propagation Delay)
30
ns
t8
Falling Edge of SCLK to Data Valid (Hold Time)
5
ns
t9
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay)
30
ns
t10
SCLK Setup Time for Synchronization or Power Down
30
ns
t11
DOUT/DRDY Pulse for Synchronization or Power Down
3 CLK
ns
t12
Rising Edge of SCLK Until Start of Synchronization
1537 CLK
7679 CLK
ns
t13
Synchronization Time
0.5 CLK
6143.5 CLK
ns
t14
Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode
2042.5 CLK
ns
t15
Rising Edge of SCLK Until Start of Power Down
7681 CLK
ns
t16
Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode
591.5 CLK
592.5 CLK
ns
t17
Falling Edge of Last DOUT/DRDY to Start of Power Down
6143.5 CLK
ns
TABLE II. Digital Timing.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1252UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1253 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER |
| ADS1253E | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit 20kHz Low Power RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1253E/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit 20kHz Low Power RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1253E/2K5G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit 20kHz Low Power RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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