參數(shù)資料
型號(hào): ADS1244IDGST
廠商: Texas Instruments
文件頁數(shù): 6/24頁
文件大?。?/td> 0K
描述: IC ADC LP 24-BIT 10-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
視頻文件: Nuts and Bolts of the Delta-Sigma Converter
標(biāo)準(zhǔn)包裝: 1
位數(shù): 24
采樣率(每秒): 15
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 270µW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,雙極
產(chǎn)品目錄頁面: 889 (CN2011-ZH PDF)
配用: 296-18359-ND - EVALUATION MODULE FOR ADS1244
其它名稱: 296-14003-6
ADS1244
14
SBAS273
www.ti.com
SINGLE-SUPPLY OPERATION
It is possible to operate the ADS1244 with a single supply.
For a 3V supply, simply connect AVDD and DVDD together.
Figure 17 shows an example of the ADS1244 running on a
single 5V supply. An external resistor, R1, is used to drop 5V
supply down to a desired voltage level of DVDD. For ex-
ample, if the desired DVDD supply voltage is 3V and AVDD
is 5V, the value of R1 should be:
R1 = (5V – 3V)/4.5
A ≈ 440k
where 4.5
A is a typical digital current consumption when
DVDD = 3V (refer to the typical characteristic “Digital Current
vs Digital Supply”). A buffer on DRDY/DOUT can provide
level-shifting if required.
DVDD can be set to a desired voltage by choosing a proper
value of R1, but keep in mind that DVDD must be set
between 1.8V and 3.6V. Note that the maximum logic HIGH
output of DRDY/DOUT is equal to DVDD, but both CLK and
SCLK inputs can be driven with 5V logic regardless of the
DVDD or AVDD voltage. Use 0.1
F capacitors to bypass
both AVDD and DVDD.
MULTICHANNEL SYSTEMS
Multiple ADS1244s can be operated in parallel to measure
multiple input signals. Figure 18 shows an example of a
2-channel system. For simplicity, the supplies and reference
circuitry were not included. The same CLK signal should be
applied to all devices. To be able to synchronize the
ADS1244s, connect the same SCLK signal to all devices as
well. When ready to synchronize, place all the devices in
Sleep Mode. Afterwards, “wakeup” and all the ADS1244s will
be synchronized. That is, they will sample the input signals
simultaneously.
The DRDY/DOUT outputs will go LOW at approximately the
same time after synchronization. The falling edges indicating
that new data is ready will vary with respect to each other no
more than timing specification t14. This variation is due to
posible differences in the ADS1244’s internal calibration
settings. To account for this when using multiple devices,
either wait for t14 to pass after seeing one device’s
DRDY/DOUT go LOW, or wait until all DRDY/DOUTs have
gone LOW before retrieving data.
FIGURE 18. Example of Using Multiple ADS1244s in Parallel.
1
2
3
4
5
10
9
8
7
6
CLK
SCLK
DRDY/DOUT
DVDD
AVDD
GND
VREFP
VREFN
AINN
AINP
ADS1244
IN1
OUT1
1
2
3
4
5
10
9
8
7
6
CLK
SCLK
DRDY/DOUT
DVDD
AVDD
GND
VREFP
VREFN
AINN
AINP
ADS1244
IN2
OUT2
CLK and SCLK
Sources
OUT1
OUT2
t
14
FIGURE 17. Example of the ADS1244 Running on a Single
5V Supply.
10
9876
1
2
345
CLK
SCLK
DRDY/DOUT
DVDD
AVDD
GND
VREFP
VREFN
AINN
AINP
ADS1244
R1
0.1
F
+5V
to +5V logic
from
+5V logic
from
+5V logic
0.1
F
++
SN74LVCC3245A
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t14
Difference between DRDY/DOUT s
±500
s
going LOW in multichannel systems.
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