To retrieve data, wait until " />
參數(shù)資料
型號(hào)： ADS1244EVM
廠商： Texas Instruments
文件頁(yè)數(shù)： 3/24頁(yè)
文件大小： 0K
描述： EVALUATION MODULE FOR ADS1244
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
視頻文件： Nuts and Bolts of the Delta-Sigma Converter
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 24
采樣率（每秒）： 15
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ 5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 150mW @ 500kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： ADS1244
已供物品： 板
產(chǎn)品目錄頁(yè)面： 889 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： ADS1244IDGSTG4-ND - IC ADC LP CONVERT 24BIT 10-MSOP
ADS1244IDGSRG4-ND - IC ADC LP CONVERT 24BIT 10-MSOP
ADS1244IDGSR-ND - IC ADC LP CONVERT 24BIT 10-MSOP
296-14003-6-ND - IC ADC LP 24-BIT 10-MSOP
296-14003-2-ND - IC ADC LP 24-BIT 10-MSOP
296-14003-1-ND - IC ADC LP 24-BIT 10-MSOP
其它名稱(chēng)： 296-18359
ADS1244
11
SBAS273
www.ti.com
DATA RETRIEVAL
The ADS1244 continuously converts the analog input signal.
To retrieve data, wait until DRDY/DOUT goes LOW, as
shown in Figure 12. After this occurs, begin shifting out the
data by applying SCLKs. Data is shifted out Most Significant
Bit (MSB) first. It is not required to shift out all the 24 bits of
data, but the data must be retrieved before the new data is
updated (see t3) or else it will be overwritten. Avoid data
retrieval during the update period. DRDY/DOUT will remain
at the state of the last bit shifted out until it is taken HIGH (see
t7), indicating that new data is being updated.
To avoid having DRDY/DOUT remain in the state of the last
bit, shift a 25th SCLK to force DRDY/DOUT HIGH, see
Figure 13. This technique is useful when a host controlling
the ADS1244 is polling DRDY/DOUT to determine when
data is ready.
FIGURE 12. Data Retrieval Timing.
DRDY/DOUT
23
22
21
124
0
LSB
MSB
Data
Data is ready.
SCLK
t
3
t
8
t
4
t
4
t
7
New data is ready.
t
5
t
6
FIGURE 13. Data Retrieval with DRDY/DOUT Forced HIGH Afterwards.
23
124
25
22
21
0
Data
25th SCLK to force DRDY/DOUT HIGH.
Data is ready.
New data is ready.
DRDY/DOUT
SCLK
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t3
DRDY/DOUT LOW to first SCLK rising edge.
0
ns
t4
SCLK positive or negative pulse width.
100
ns
t5(1)
SCLK rising edge to new data bit valid:
50
ns
propagation delay.
t6
SCLK rising edge to old data bit valid: hold time.
0
ns
t7(2)
Data updating, no read back allowed.
152
s
t8(2)
Conversion time (1/data rate).
66.667
ms
NOTES: (1) Load on DRDY/DOUT = 20pF || 100k
. (2) Values given for f
CLK = 2.4576MHz. For different
CLK frequencies, scale proportional to CLK period. For example, for fCLK = 4.9152MHz, t8 → 33.333ms.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1244-EVM 制造商:BB 制造商全稱(chēng):BB 功能描述:Low-Power, 24-Bit ANALOG-TO-DIGITAL CONVERTER
ADS1244IDGSR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1244IDGSRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1244IDGST 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1244IDGSTG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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