ELECTRICAL CHARACTERISTICS: AVDD = 5V
參數(shù)資料
型號： ADS1240E
廠商： Texas Instruments
文件頁數(shù)： 23/30頁
文件大?。?/td> 0K
描述： IC ADC 24-BIT SER PROGBL 24-SSOP
產(chǎn)品培訓模塊： Data Converter Basics
視頻文件： Nuts and Bolts of the Delta-Sigma Converter
標準包裝： 60
位數(shù)： 24
采樣率（每秒）： 15
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.9mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.209"，5.30mm 寬）
供應商設備封裝： 24-SSOP
包裝： 管件
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極
產(chǎn)品目錄頁面： 889 (CN2011-ZH PDF)
其它名稱： 296-9301-5
296-9301-5-ND
ADS1240, 1241
3
SBAS173F
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +2.5V, unless otherwise specified.
ADS1240
ADS1241
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0 – AIN7, AINCOM)
Analog Input Range
Buffer OFF
AGND – 0.1
AVDD + 0.1
V
Buffer ON
AGND + 0.05
AVDD – 1.5
V
Full-Scale Input Range
(In+) – (In–), See Block Diagram, RANGE = 0
±V
REF /PGA
V
RANGE = 1
±V
REF /(2 PGA)
V
Differential Input Impedance
Buffer OFF
5/PGA
M
Buffer ON
5
G
Bandwidth
fDATA = 3.75Hz
–3dB
1.65
Hz
fDATA = 7.50Hz
–3dB
3.44
Hz
fDATA = 15.00Hz
–3dB
14.6
Hz
Programmable Gain Amplifier
User-Selectable Gain Ranges
1
128
Input Capacitance
9pF
Input Leakage Current
Modulator OFF, T = 25
°C5
pA
Burnout Current Sources
2
A
OFFSET DAC
Offset DAC Range
RANGE = 0
±V
REF /(2 PGA)
V
RANGE = 1
±V
REF /(4 PGA)
V
Offset Monotonicity
8
Bits
Offset DAC Gain Error
±10
%
Offset DAC Gain Error Drift
1
ppm/
°C
SYSTEM PERFORMANCE
Resolution
No Missing Codes
24
Bits
Integral Nonlinearity
End Point Fit
±0.0015
% of FS
Offset Error (1)
7.5
ppm of FS
Offset Drift(1)
0.02
ppm of FS/
°C
Gain Error
0.005
%
Gain Error Drift(1)
0.5
ppm/
°C
Common-Mode Rejection
at DC
100
dB
fCM = 60Hz, fDATA = 15Hz
130
dB
fCM = 50Hz, fDATA = 15Hz
120
dB
Normal-Mode Rejection
fSIG = 50Hz, fDATA = 15Hz
100
dB
fSIG = 60Hz, fDATA = 15Hz
100
dB
Output Noise
See Typical Characteristics
Power-Supply Rejection
at DC, dB = –20 log(
V
OUT /VDD)
(2)
80
95
dB
VOLTAGE REFERENCE INPUT
VREF
VREF ≡ (REF IN+) – (REF IN–), RANGE = 0
0.1
2.5
2.6
V
Reference Input Range
REF IN+, REF IN–
0
AVDD
V
RANGE = 1
0.1
AVDD
V
Common-Mode Rejection
at DC
120
dB
Common-Mode Rejection
fVREFCM = 60Hz, fDATA = 15Hz
120
dB
Bias Current(3)
VREF = 2.5V
1.3
A
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
AVDD
4.75
5.25
V
Analog Current
PDWN = 0, or SLEEP
1
nA
PGA = 1, Buffer OFF
120
250
A
PGA = 128, Buffer OFF
400
675
A
PGA = 1, Buffer ON
160
300
A
PGA = 128, Buffer ON
760
1275
A
Digital Current
Normal Mode, DVDD = 5V
80
125
A
SLEEP Mode, DVDD = 5V
60
A
Read Data Continuous Mode, DVDD = 5V
230
A
PDWN
0.5
nA
Power Dissipation
PGA = 1, Buffer OFF, DVDD = 5V
1.1
1.9
mW
NOTES: (1) Calibration can minimize these errors to the level of the noise.
(2)
V
OUT is a change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
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