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參數(shù)資料
| 型號： | ADS1232IPWRG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 8/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24-BIT 10/80SPS 24-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 10，80 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 13.1mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，雙極 |
| 配用： | 296-20803-ND - EVALUATION MODULE FOR ADS1232 |
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FREQUENCY RESPONSE
Frequency (kHz)
G
a
in
(d
B
)
0
20
40
60
80
100
120
140
160
180
200
38.4
76.8
0
f
CLK = 4.9152MHz
Frequency (Hz)
G
a
in
(d
B
)
0
50
100
150
0
10
20
30
40
50
60
70
80
90
100
(a)
Frequency (Hz)
(b)
G
a
in
(d
B
)
50
100
150
49
48
46 47
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Data Rate = 10SPS
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
Figure 31(b) shows the zoom in plot for both 50Hz
and 60Hz notches with the SPEED pin tied low
The ADS1232/4 use a sinc4 digital filter with the
(10SPS data rate). With only a ±3% variation of the
frequency response (fCLK = 4.9152MHz) shown in
internal
oscillator,
over
100dB
of
normal-mode
Figure 30. The frequency response repeats at
rejection is achieved.
multiples of the modulator sampling frequency of
76.8kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 3.32Hz with the
SPEED pin tied low (10SPS data rate) and 11.64Hz
with the SPEED pin tied high (80SPS data rate).
Figure 30. Frequency Response
To help see the response at lower frequencies,
Figure 31(a) illustrates the response out to 100Hz,
when the data rate = 10SPS. Notice that signals at
multiples
of
10Hz
are
rejected,
and
therefore
simultaneous rejection of 50Hz and 60Hz is achieved.
The benefit of using a sinc4 filter is that every
Figure 31. Frequency Response Out To 100Hz
frequency notch has four zeros on the same location.
This response, combined with the low drift internal
oscillator,
provides
an
excellent
normal-mode
The ADS1232/4 data rate and frequency response
rejection of line-cycle interference.
scale directly with clock frequency. For example, if
fCLK increases from 4.9152MHz to 6.144MHz when
the SPEED pin is tied high, the data rate increases
from 80SPS to 100SPS, while notches also increase
from 80Hz to 100Hz. Note that this is only possible
when the external clock source is applied.
16
Copyright 2005–2008, Texas Instruments Incorporated
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