參數(shù)資料
型號(hào): ADS1232IPWR
廠商: Texas Instruments
文件頁(yè)數(shù): 14/39頁(yè)
文件大?。?/td> 0K
描述: IC ADC 24-BIT 10/80SPS 24-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
視頻文件: Nuts and Bolts of the Delta-Sigma Converter
標(biāo)準(zhǔn)包裝: 1
位數(shù): 24
采樣率(每秒): 10,80
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 13.1mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,雙極
其它名稱: 296-25894-6
www.ti.com
STANDBY MODE
DRDY/DOUT
23
22
21
1
24
0
23
SCLK
Standby Mode
Start Conversion
Data Ready
t
9
t
10
t
11
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
When t10 has passed with SCLK held high, Standby
mode will activate. DRDY/DOUT stays high when
Standby
mode
dramatically
reduces
power
Standby mode begins. SCLK must remain high to
consumption by shutting down most of the circuitry. In
stay in Standby mode. To exit Standby mode
Standby mode, the entire analog circuitry is powered
(wakeup), set SCLK low. The first data after exiting
down and only the clock source circuitry is awake to
Standby mode is valid.
reduce the wake-up time from the Standby mode. To
enter Standby mode, simply hold SCLK high after
DRDY/DOUT goes low; see Figure 37. Standby mode
can be initiated at any time during readback; it is not
necessary to retrieve all 24 bits of data beforehand.
Figure 37. Standby Mode Timing (can be used for single conversions)
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
SPEED = 1
0
12.44
ms
SCLK high after DRDY/DOUT goes low
t9
(1)
to activate Standby mode
SPEED = 0
0
99.94
ms
SPEED = 1
12.46
ms
t10
(1)
Standby mode activation time
SPEED = 0
99.96
ms
SPEED = 1
52.51
ms
t11
(1)
Data ready after exiting Standby mode
SPEED = 0
401.8
ms
(1)
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
Copyright 2005–2008, Texas Instruments Incorporated
21
Product Folder Link(s): ADS1232 ADS1234
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