參數(shù)資料
型號(hào)： ADS1232IPWG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 11/39頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24-BIT 10/80SPS 24-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
視頻文件： Nuts and Bolts of the Delta-Sigma Converter
標(biāo)準(zhǔn)包裝： 60
位數(shù)： 24
采樣率（每秒）： 10，80
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 13.1mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸入數(shù)目和類型： 4 個(gè)單端，單極；2 個(gè)差分，雙極
配用： 296-20803-ND - EVALUATION MODULE FOR ADS1232
www.ti.com
DATA RETRIEVAL
DRDY/DOUT
23
22
21
1
24
0
LSB
MSB
Data
Data Ready
SCLK
t
2
t
7
t
3
t
3
t
6
New Data Ready
t
4
t
5
23
1
24
25
22
21
0
Data
25th SCLK to Force DRDY/DOUT High
Data Ready
New Data Ready
DRDY/DOUT
SCLK
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
indicating that new data are being updated. To avoid
having DRDY/DOUT remain in the state of the last
The ADS1232/4 continuously convert the analog
bit, the user can shift SCLK to force DRDY/DOUT
input signal. To retrieve data, wait until DRDY/DOUT
high, as shown in Figure 35. This technique is useful
goes low, as shown in Figure 34. After this occurs,
when
a
host
controlling
the
device
is
polling
begin shifting out the data by applying SCLKs. Data
DRDY/DOUT to determine when data are ready.
are shifted out MSB first. It is not required to shift out
all 24 bits of data, but the data must be retrieved
before new data are updated (within t7) or else it will
be overwritten. Avoid data retrieval during the update
period (t6). DRDY/DOUT remains at the state of the
last bit shifted out until it is taken high (see t6),
Figure 34. Data Retrieval Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t2
DRDY/DOUT low to first SCLK rising edge
0
ns
t3
SCLK positive or negative pulse width
100
ns
SCLK rising edge to new data bit valid: propagation
t4
50
ns
delay
t5
SCLK rising edge to old data bit valid: hold time
0
ns
t6
(1)
Data updating: no readback allowed
39
s
SPEED = 1
12.5
ms
t7
(1)
Conversion time (1/data rate)
SPEED = 0
100
ms
(1)
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period.
Figure 35. Data Retrieval with DRDY/DOUT Forced High Afterwards
Copyright 2005–2008, Texas Instruments Incorporated
19
Product Folder Link(s): ADS1232 ADS1234
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1232IPWR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Ultra Low-Noise RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1232IPWRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Ultra Low-Noise RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1232REF 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1232REF Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS1234 制造商:BB 制造商全稱:BB 功能描述:Ultra Low-Noise, 24-Bit Analog-to-Digital Converter
ADS1234IPW 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Ultra Low-Noise RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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