參數(shù)資料
型號: ADS1203IPWR
英文描述: MOTOR CONTROL CURRENT MEASUREMENT
中文描述: 電機控制電流測量
文件頁數(shù): 14/24頁
文件大小: 276K
代理商: ADS1203IPWR
SBAS318 JUNE 2004
www.ti.com
14
R
SW
350
(typ)
Switching Frequency
= CLK
High
Impedance
> 1G
C
7pF (typ)
V
CM
A
IN
+
R
SW
350
(typ)
High
Impedance
> 1G
C
7pF (typ)
1.5pF
1.5pF
A
IN
Figure 6. Input Impedance of the ADS1203
Modulator
The ADS1203 can be operated in four modes. Modes
0, 1, and 2 use the internal clock, which is fixed at
20MHz. The modulator can also be operated with an
external clock in mode 3. In all modes, the clock is
divided by 2 internally and is used as the modulator
clock. The frequency of the external clock can vary from
1MHz to 32MHz to adjust for the clock requirements of
the application.
The modulator topology is fundamentally a 2nd-order,
switched-capacitor, delta-sigma modulator, such as the
one conceptualized in Figure 7. The analog input
voltage and the output of the 1-bit digital-to-analog
converter (DAC) are differentiated, providing analog
voltages at X2 and X3. The voltages at X2 and X3 are
presented to their individual integrators. The output of
these integrators progress in a negative or positive
direction. When the value of the signal at X4 equals the
comparator reference voltage, the output of the
comparator switches from negative to positive, or
positive to negative, depending on its original state.
When the output value of the comparator switches from
high to low or vice versa, the 1-bit DAC responds on the
next clock pulse by changing its analog output voltage
at X6, causing the integrators to progress in the
opposite direction. The feedback of the modulator to the
front end of the integrators forces the value of the
integrator output to track the average of the input.
V
REF
X
4
X
6
Integrator 2
Comparator
f
CLK
DATA
D/A Converter
X
3
X
2
X(t)
f
S
Integrator 1
Figure 7. Block Diagram of the 2nd-Order Modulator
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