參數(shù)資料
型號(hào)： ADP5024ACPZ-1-R7
廠商： ANALOG DEVICES INC
元件分類： 穩(wěn)壓器
英文描述： SWITCHING REGULATOR, PQCC24
封裝： 4 X 4 MM, ROHS COMPLIANT, MO-220, LCC-24
文件頁(yè)數(shù)： 9/27頁(yè)
文件大小： 926K
代理商： ADP5024ACPZ-1-R7
Preliminary Technical Data
ADP5024
Rev. PrA | Page 17 of 27
THEORY OF OPERATION
ENABLE
& MODE
CONTROL
LDO
CONTROL
LDO
UNDERVOLTAGE
LOCK OUT
SOFT START
PWM/
PSM
CONTROL
BUCK2
DRIVER
AND
ANTISHOOT
THROUGH
SOFT START
PWM/
PSM
CONTRO
L
BUCK1
DRIVER
AND
ANTISHOOT
THROUGH
OSCILLATOR
THERMAL
SHUTDOWN
SYSTEM
UNDERVOLTAGE
LOCK OUT
PWM
COMP
GM ERROR
AMP
GM ERROR
AMP
PSM
COMP
PSM
COMP
LOW
CURRENT
I LIMIT
PWM
COMP
LOW
CURRENT
I LIMIT
R1
R2
ADP5024
VOUT1
VOUT2
VIN1
SW1
PGND1
EN1
VIN3
AGND
VOUT3
MODE
PGND2
SW2
VIN2
AVIN
ENBK1
ENBK2
ENLDO
Mode2
sel
Y
A
B
OpMode
ENBK1
ENBK2
ENLDO
EN2
EN3
FB3
FB1 FB2
AVIN
600
75
Figure 45. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5024 is a micropower management units (micro
PMU) combing two step-down (buck) dc-to-dc convertors
and one low dropout linear regulators (LDO). The high
switching frequency and tiny 24-lead LFCSP package allow
for a small power management solution.
To combine these high performance regulators into the micro
PMU, there is a system controller allowing them to operate
together.
The buck regulators can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
buck switching frequency is always constant and does not
change with the load current. If the MODE pin is at logic low
level, the switching regulators operate in auto PWM/PSM
mode. In this mode, the regulators operate at fixed PWM
frequency when the load current is above the PSM current
threshold. When the load current falls below the PSM current
threshold, the regulator in question enters PSM, where the
switching occurs in bursts. The burst repetition rate is a
function of the current load and the output capacitor value.
This operating mode reduces the switching and quiescent
current losses. The auto PWM/PSM mode transition is
controlled independently for each buck regulator. The two
bucks operate synchronized to each other.
The ADP5024 has individual enable pins (EN1 to EN3)
controlling the activation of each regulator. The regulators are
activated by a logic level high applied to the respective EN pin.
EN1 controls BUCK1, EN2 controls BUCK2, EN3 controls
LDO.
Regulator output voltages are set through external resistor
dividers or can be optionally factory programmed to default
values (see the Ordering Guide section).
When a regulator is turned on, the output voltage ramp rate is
controlled though a soft start circuit to avoid a large inrush
current due to the charging of the output capacitors.
Thermal Protection
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off all the regulators.
Extreme junction temperatures can be the result of high
current operation, poor circuit board design, or high ambient
temperature. A 20°C hysteresis is included so that when
thermal shutdown occurs, the regulators do not return to
operation until the on-chip temperature drops below 130°C.
When coming out of thermal shutdown, all regulators re-start
with soft-start control.
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