參數(shù)資料
型號(hào): ADP3415
廠商: Analog Devices, Inc.
英文描述: Dual MOSFET Driver with Bootstrapping
中文描述: 與自舉雙MOSFET驅(qū)動(dòng)器
文件頁數(shù): 2/12頁
文件大?。?/td> 166K
代理商: ADP3415
REV. B
–2–
ADP3415–SPECIFICATIONS
1
(T
= 0 C to 100 C, V
= 5 V, V
BST
– V
SW
= 5 V,
SD
= 5 V, C
DRVH
= C
DRVL
= 3 nF,
unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY (VCC)
Quiescent Current
2
Shutdown Mode
Operating Mode
I
CCQ
V
SD
= 0.8 V
V
SD
= 5 V, No Switching
30
1.2
65
2
μ
A
mA
UNDERVOLTAGE LOCKOUT
(UVLO)
UVLO Threshold
UVLO Hysteresis
V
CCUVLO
V
CCHUVLO
3.9
4.15
0.05
4.5
V
V
LOW-SIDE DRIVER SHUTDOWN
(
DRVLSD
)
Input Voltage High
3
Input Voltage Low
3
Propagation Delay
3, 4
(See Figure 3)
V
IH
V
IL
tpdl
DRVLSD
tpdh
DRVLSD
2.0
V
V
ns
ns
0.8
50
30
20
10
SHUTDOWN (
SD
)
Input Voltage High
3
Input Voltage Low
3
V
IH
V
IL
2.0
V
V
0.8
INPUT (IN)
Input Voltage High
3
Input Voltage Low
3
V
IH
V
IL
2.0
V
V
0.8
THERMAL SHUTDOWN (THSD)
THSD Threshold
THSD Hysteresis
T
SD
T
HSD
T
J
= T
A
T
J
= T
A
165
10
°
C
°
C
HIGH-SIDE DRIVER (DRVH)
Output Resistance, DRVH
BST
Output Resistance, DRVH
SW
DRVH Transition Times
4
(See Figure 4)
DRVH Propagation Delay
4, 5
1.5
0.85
20
25
22
3.5
2.0
30
35
40
200
70
ns
ns
ns
ns
ns
tr
DRVH
tf
DRVH
tpdh
DRVH
V
BST
V
SW
= 4.6 V
V
BST
V
SW
= 4.6 V, V
DLY
= 0 V
R
DLY
120 k
10
100
(See Figure 4)
tpdl
DRVH
40
LOW-SIDE DRIVER (DRVL)
Output Resistance, DRVL
VCC
Output Resistance, DRVL
GND
DRVL Transition Times
4
(See Figure 4)
DRVL Propagation Delay
4, 5, 6
(See Figure 4)
SW Transition Timeout
7
Zero-Crossing Threshold
1.6
1.0
25
20
30
10
3.0
3.0
40
30
38
25
300
ns
ns
ns
ns
ns
V
tr
DRVL
tf
DRVL
tpdh
DRVL
tpdl
DRVL
t
SWTO
V
ZC
V
BST
V
SW
= 4.6 V
V
BST
V
SW
= 4.6 V
V
BST
V
SW
= 4.6 V
V
BST
V
SW
= 4.6 V
V
BST
V
SW
= 4.6 V
10
130
1.6
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Including I
BSTQ
quiescent current.
3
The signal source driving the pin must have 70
μ
A (typ) pull-down strength to make a high-to-low transient, and 20
μ
A (typ) pull-up strength to make a low-to-high
transient. The pin does not represent load (<100 nA) in static low (<0.8 V) and static high (>2.0 V) logic states (see TPC 3.) The pin can be driven with standard
TTL logic level source.
4
Guaranteed by characterization.
5
For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low.
6
Propagation delay measured until DRVL begins its transition.
7
The turn-on of DRVL is initiated after IN goes low by either V
SW
crossing a ~1.6 V threshold or by expiration of t
SWTO
.
Specifications subject to change without notice.
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