參數(shù)資料
型號(hào): ADP3413JR
廠商: ANALOG DEVICES INC
元件分類: MOSFETs
英文描述: Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-SM8 -40 to 110
中文描述: HALF BRDG BASED MOSFET DRIVER, PDSO8
封裝: MS-012AA, SOIC-8
文件頁(yè)數(shù): 3/8頁(yè)
文件大?。?/td> 142K
代理商: ADP3413JR
REV. 0
–3–
ADP3413
PIN CONFIGURATION
IN
VCC
BST
DRVH
SW
DRVL
PGND
8
7
6
5
1
2
3
4
ADP3413
(TOP VIEW
OD
ABSOLUTE MAXIMUM RATINGS
*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.3 V to +8 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.3 V to +8 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0 V to +25 V
OD
, IN . . . . . . . . . . . . . . . . . . . . . . . .
0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0
°
C to 70
°
C
Operating Junction Temperature Range . . . . . . 0
°
C to 125
°
C
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
°
C/W
θ
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
°
C/W
Storage Temperature Range . . . . . . . . . . . .
65
°
C to +150
°
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300
°
C
*
This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3413 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
BST
Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW pins
holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be
chosen between 100 nF and 1 F.
TTL-level Input Signal, which has primary control of the drive outputs.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with ~1
μ
F ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
This pin is connected to the buck-switching node, close to the upper MOSFET
s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-
on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the
high-low transition delay is determined at this pin.
Buck Drive. Output drive for the upper (buck) MOSFET.
2
3
4
5
6
7
IN
OD
VCC
DRVL
PGND
SW
8
DRVH
ORDERING GUIDE
Temperature Package
Range
Package
Option
Model
Description
ADP3413JR 0
°
C to 70
°
C
8-Lead Standard
Small Outline (SOIC)
SO-8
相關(guān)PDF資料
PDF描述
ADP3414 Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-SM8 -40 to 110
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