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參數(shù)資料
| 型號(hào)： | ADP3410 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual MOSFET Driver with Bootstrapping |
| 中文描述： | 與自舉雙MOSFET驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大小： | 148K |
| 代理商： | ADP3410 |
REV. 0
ADP3410
–9–
delay from the
DRVLSD
input to the DRVL output is about
30 ns.
Synchronous Rectifier Monitor
The synchronous rectifier monitor provides a TTL output signal
for use by the PWM controller. The SRMON output follows the
DRVL signal when the low-side driver is enabled and goes high
when the low-side driver is shut down.
Shutdown
The shutdown input is used for power management. If the cir-
cuits running off of the buck converter are not needed, the
ADP3410 can be shut down to conserve power.
When the
SD
pin is high, the ADP3410 is enabled for normal
operation. Pulling the
SD
pin low forces the VCCGD, DRVH
and DRVL outputs low turning the buck converter OFF and
reducing the VCC
supply current to less than 10
μ
A.
Undervoltage Lockout
The undervoltage lockout (UVLO) circuit holds both FET
driver outputs low during VCC
supply ramp up. The UVLO
logic becomes active and in control of the driver outputs at a
supply voltage of 1.5 V. The UVLO circuit will wait until the
VCC
supply has reached a voltage high enough to bias logic
level FETs fully ON, around 4.4 V, before releasing control
of the drivers to the PWM input.
VCC Good
The power ready signal, VCCGD, indicates the status of the
VCC
supply. When the device is in UVLO, the VCCGD output
is pulled low by an NMOS transistor. Upon exiting UVLO mode,
the VCCGD pin is pulled up to VCC
with a 5
PMOS transis-
tor capable of sourcing current to external load circuits. As can
be seen from the block diagram, the UVLO comparator output
and the
SD
signal are ANDed together to become the VCCGD
output, so when the device is put into shutdown the VCCGD
output will be low regardless of the VCC voltage.
Thermal Shutdown
The thermal shutdown circuit protects the ADP3410 against
damage due to excessive power dissipation. Under extreme
conditions, high ambient temperature and high-power dissipation,
the die temperature can rise up to the over-temperature trip
point of 165
°
C. If the die temperature exceeds 165
°
C, the
thermal shutdown circuit will turn the output drivers OFF. The
drivers will remain disabled until the junction temperature has
decreased by 10
°
C, at which point the drivers are enabled again.
APPLICATION INFORMATION
Supply Capacitor Selection
For the supply input (VCC) of the ADP3410, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 5
μ
F to 10
μ
F, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size and can be
obtained from the following vendors:
Murata
GRM235Y5V106Z16 http://www.murata.com
Taiyo-Yuden EMK325F106ZF
Tokin
C23Y5V1C106ZP
http://www.t-yuden.com
http://www.tokin.com
A lower cost alternative may be to use a 5
μ
F to 10
μ
F tantalum
capacitor with a small (1
μ
F) ceramic in parallel. Keep the
ceramic capacitor as close as possible to the ADP3410.
Bootstrap Circuit
The bootstrap circuit requires a charge storage capacitor, C
BST
,
and a Schottky diode, D1, as shown in Figure 2. Selecting these
components can be done after the high-side FET has been chosen.
The bootstrap capacitor must have a voltage rating that is able
to handle the maximum battery voltage plus 5 V. A minimum
50 V rating is recommended. The capacitance is determined
using the following equation:
C
Q
V
BST
GATE
BST
=
(1)
where
Q
GATE
is the total gate charge of the high-side FET, and
V
BST
is the voltage droop allowed on the high-side FET drive.
For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required bootstrap
capacitance is 100 nF. Look for a good quality ceramic capacitor.
A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high-side FET. The bootstrap diode must have a minimum
40 V rating to withstand the maximum battery voltage plus 5 V.
The average forward current can be estimated by:
I
Q
f
F AVG
GATE
MAX
)
≈
×
(2)
where
f
MAX
is the maximum switching frequency of the controller.
The peak surge current rating should be checked in circuit since
this is dependent on the source impedance of the 5 V supply,
and the ESR of C
BST
.
Setting the OVP Threshold
The ADP3410 can shut down the high-side FET drive when the
OVPSET input exceeds the threshold voltage. The voltage at
which V
OUT
trips the overvoltage protection is set by selecting
the values for Ra and Rb shown in Figure 2. The threshold for
the OVP is calculated using:
V
V
Ra
Rb
OVP
=
×
+
1 2
.
1
(3)
where
V
OVP
is the desired OVP threshold voltage at V
OUT
.
In order to minimize the bias current error, Rb should be less
than or equal to 24 k
. By selecting a value for Rb
≤
24 k
and
solving for Ra gives the following formula:
Ra
V
V
Rb
OVP
.
=
×
1 2
1
(4)
Note that the minimum the OVP threshold can be is 1.2 V when
Ra is zero.
Delay Capacitor Selection
The delay capacitor, C
DLY
, is used to add an additional delay
when the low-side FET drive turns off and when the high-side
drive starts to turn on. The delay capacitor adds 1 ns/pF of
additional time to the 20 ns of fixed delay.
If a delay capacitor is required, a good quality ceramic capacitor
with an NPO or COG dielectric or a good quality mica capacitor
should be used. Both types of capacitors are available in the
1 pF to 100 pF range and have excellent temperature and
leakage characteristics.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADP3412 | Replaced by BQ29415 : Voltage Protection for 2, 3, or 4 Cell LiIon Batteries (2nd Lev Protection) 8-SM8 -25 to 85 |
| ADP3412JR | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-SM8 -40 to 110 |
| ADP3413 | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-SM8 -40 to 110 |
| ADP3413JR | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-SM8 -40 to 110 |
| ADP3414 | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-SM8 -40 to 110 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADP34100002RUR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADP34100003RUR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADP3410KRU | 制造商:Analog Devices 功能描述:Single MOSFET DRIVER, 14 Pin, Plastic, TSSOP |
| ADP3410KRU-REEL | 功能描述:IC MOSFET DVR DUAL N-CH 14TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 外部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 配置:高端 輸入類型:非反相 延遲時(shí)間:200ns 電流 - 峰:250mA 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動(dòng)）:600V 電源電壓:12 V ~ 20 V 工作溫度:-40°C ~ 125°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-DIP 包裝:管件 其它名稱:*IR2127 |
| ADP3410KRU-REEL7 | 功能描述:IC MOSFET DVR DUAL N-CH 14TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 外部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 配置:高端 輸入類型:非反相 延遲時(shí)間:200ns 電流 - 峰:250mA 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動(dòng)）:600V 電源電壓:12 V ~ 20 V 工作溫度:-40°C ~ 125°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-DIP 包裝:管件 其它名稱:*IR2127 |
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