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參數(shù)資料
| 型號： | ADP3335ARM-285 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 639K |
| 代理商： | ADP3335ARM-285 |
ADP3335
–7–
REV. 0
It is important to note that as C
NR
increases, the turn-on time
will be delayed. With NR values greater than 1 nF, this delay
may be on the order of several milliseconds.
V
IN
V
OUT
ADP3335
ON
OFF
SD
GND
C
1 F
+
NR
C
NR
OUT
OUT
OUT
IN
IN
C
IN
1 F
+
Figure 21. Typical Application Circuit
Paddle-Under-Lead Package
The ADP3335 uses a patented paddle-under-lead package
design to ensure the best thermal performance in an MSOP-8
footprint. This new package uses an electrically isolated die
attach that allows all pins to contribute to heat conduction.
This technique reduces the thermal resistance to 110
°
C/W on a
4-layer board as compared to >160
°
C/W for a standard MSOP-8
leadframe. Figure 22 shows the standard physical construc-
tion of the MSOP-8 and the paddle-under-lead leadframe.
DIE
Figure 22. Thermally Enhanced Paddle-Under-Lead Package
Thermal Overload Protection
The ADP3335 is protected against damage from excessive power
dissipation by its thermal overload protection circuit which limits
the die temperature to a maximum of 165
°
C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165
°
C, the output
current is reduced until the die temperature has dropped to a
safe level. The output current is restored when the die tempera-
ture is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150
°
C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
(
Where
I
LOAD
and
I
GND
are load current and ground current,
V
IN
and
V
OUT
are input and output voltages respectively.
Assuming I
LOAD
= 400 mA, I
GND
= 4 mA, V
IN
= 5.0 V and
V
OUT
= 3.3 V, device power dissipation is:
P
D
= (5 – 3.3) 400
mA
+ 5.0(4
mA
) = 700
mW
The proprietary package used in the ADP3335 has a thermal
resistance of 110
°
C/W, significantly lower than a standard
MSOP-8 package. Assuming a 4-layer board, the junction tem-
perature rise above ambient temperature will be approximately
equal to:
P
V
V
I
V
I
D
IN
OUT
LOAD
IN
GND
=
)
+
(
)
T
W
C W
°
/
C
°
A
J
=
×
=
0 700
.
110
77 0
.
To limit the maximum junction temperature to 150
°
C, maxi-
mum allowable ambient temperature will be:
T
AMAX
= 150
°
C
–
77.0
°
C
= 73.0
°
C
Printed Circuit Board Layout Consideration
All surface mount packages rely on the traces of the PC board to
conduct heat away from the package.
In standard packages the dominant component of the heat resis-
tance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement mean-
ingful, however, a significant copper area on the PCB must be
attached to these fused pins.
The patented paddle-under-lead frame design of the ADP3335
uniformly minimizes the value of the dominant portion of the
thermal resistance. It ensures that heat is conducted away by all
pins of the package. This yields a very low 110
°
C/W thermal
resistance for an MSOP-8 package, without any special board
layout requirements, relying only on the normal traces connected
to the leads. This yields a 33% improvement in heat dissipation
capability as compared to a standard MSOP-8 package. The
thermal resistance can be decreased by, approximately, an addi-
tional 10% by attaching a few square cm of copper area to the
IN pin of the ADP3335 package.
It is not recommended to use solder mask or silkscreen on the
PCB traces adjacent to the ADP3335
’
s pins since it will increase
the junction-to-ambient thermal resistance of the package.
Shutdown Mode
Applying a TTL high signal to the shutdown (
SD
) pin or tying
it to the input pin, will turn the output ON. Pulling
SD
down to
0.4 V or below, or tying it to ground will turn the output OFF.
In shutdown mode, quiescent current is reduced to much less
than 1
μ
A.
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