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參數資料
| 型號： | ADP3330ART-285 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護 |
| 文件頁數： | 8/12頁 |
| 文件大?。?/td> | 137K |
| 代理商： | ADP3330ART-285 |
ADP3330
–8–
REV. A
APPLICATION INFORMATION
Capacitor Selection
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3330 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 0.47
μ
F is all that is
needed for stability; larger capacitors can be used if high output
current surges are anticipated. The ADP3330 is stable with
extremely low ESR capacitors (ESR
≈
0), such as Multilayer
Ceramic Capacitors (MLCC) or OSCON. Note that the
effective capacitance of some capacitor types may fall below the
minimum at cold temperature. Ensure that the capacitor
provides more than 0.47
μ
F at minimum temperature.
Input Bypass Capacitor: an input bypass capacitor is not strictly
required but it is advisable in any application involving long
input wires or high source impedance. Connecting a 0.47
μ
F
capacitor from IN to ground reduces the circuit’s sensitivity to
PC board layout. If a larger value output capacitor is used, then
a larger value input capacitor is also recommended.
Noise Reduction
A noise reduction capacitor (C
NR
) can be used to further reduce
the noise by 6 dB–10 dB (Figure 21). Low leakage capacitors in
10 pF–500 pF range provide the best performance. Since the
noise reduction pin (NR) is internally connected to a high imped-
ance node, any connection to this node should be carefully done
to avoid noise pickup from external sources. The pad connected
to this pin should be as small as possible and long PC board
traces are not recommended.
When adding a noise reduction capacitor, use the following
guidelines:
Maintain a minimum load current of 1 mA when not in
shutdown.
For CNR values greater than 500 pF, add a 100 k
series
resistor (RNR).
It is important to note that as CNR increases, the turn-on time
will be delayed. With CNR values greater than 1 nF, this delay
may be on the order of several milliseconds.
+
–
V
IN
+
–
C1
0.47
m
F
IN
ADP3330-3
SD
GND
V
OUT
= +3.3V
OUT
330k
V
C2
0.47
m
F
R1
CNR
RNR
NR
ERR
Figure 21.Noise Reduction Circuit
Chip-on-Lead Package
The ADP3330 uses a patented Chip-on-Lead package design to
ensure the best thermal performance in an SOT-23 footprint. In
a standard SOT-23, the majority of the heat flows out of the
ground pin. This new package uses an electrically isolated die
attach that allows all pins to contribute to heat conduction.
This technique reduces the thermal resistance to 190
°
C/W on a
2-layer board as compared to >230
°
C/W for a standard SOT-23
leadframe. Figure 22 shows the difference between the standard
SOT-23 and the Chip-on-Lead leadframes.
SILICON
DIE
a. Normal SOT-23-6 Package
SILICON DIE WITH
ELECTRICALLY
ISOLATED
DIE ATTACH
b. Thermally Enhanced Chip-on-Lead Package
Figure 22.
Thermal Overload Protection
The ADP3330 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit
which limits the die temperature to a maximum of +165
°
C.
Under extreme conditions (i.e., high ambient temperature and
power dissipation) where die temperature starts to rise above
+165
°
C, the output current is reduced until the die temperature
has dropped to a safe level. The output current is restored when
the die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed +125
°
C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
P
D
=
(
V
IN
– V
OUT
)
I
LOAD
+(
V
IN
)
I
GND
Where
I
LOAD
and
I
GND
are load current and ground current,
V
IN
and
V
OUT
are input and output voltages respectively.
Assuming
I
LOAD
= 200 mA,
I
GND
= 4 mA,
V
IN
= 4.2 V and
V
OUT
= 3.0 V, device power dissipation is:
P
D
=
(4.2
–
3)
200
mA +
4.2
(4
mA
)
= 257
mW
The proprietary package used in the ADP3330 has a thermal
resistance of 165
°
C/W, significantly lower than a standard
6-lead SOT-23 package. Assuming a 4-layer board, the junction
temperature rise above ambient temperature will be approxi-
mately equal to:
T
J
A
= 0.257
W
×
165
°
C/W
= 42.4
°
C
To limit the maximum junction temperature to +125
°
C,
maximum allowable ambient temperature will be:
T
A MAX
= 125
°
C
– 42.4
°
C
= 82.6
°
C
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADP3330ART-3 | 制造商:Analog Devices 功能描述: |
| ADP3330ART3.3 | 制造商:ANALOG 功能描述:IC |
| ADP3330ART-3.3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Positive Fixed Voltage Regulator |
| ADP3330ART-3.3-RL | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:IC,VOLT REGULATOR,FIXED,+3.3V,BIPOLAR,TSOP,6PIN,PLASTIC |
| ADP3330ART-3.3-RL7 | 功能描述:IC REG LDO 3.3V .2A SOT-23-6 RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性 系列:anyCAP® 標準包裝:3,000 系列:- 穩(wěn)壓器拓撲結構:正，固定式和可調式 輸出電壓:3.3V，1.25 V ~ 5.7 V 輸入電壓:4.5 V ~ 7 V 電壓 - 壓降（標準）:1.1V @ 1A 穩(wěn)壓器數量:2 電流 - 輸出:1A 電流 - 限制（最小）:1A 工作溫度:0°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:TO-252-5，DPak（4 引線 + 接片），TO-252AD 供應商設備封裝:PPAK 包裝:管件 其它名稱:497-3576-5 |
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