
6-Bit, Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller
ADP3168
FEATURES
Rev.
B
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Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase
±10 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to
external high power drivers
Active current balancing between all output phases
Built-in Power Good/crowbar blanking supports
On-the-fly VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with
programmable latch-off delay
APPLICATIONS
Desktop PC power supplies for:
Next generation Intel processors
VRM modules
GENERAL DESCRIPTION
The ADP3168 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 6-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between
0.8375 V and 1.6 V, and uses a multimode PWM architecture to
drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency. The
phase relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation, allowing for the construc-
tion of up to four complementary buck switching stages.
The ADP3168 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a
system transient. The ADP3168 also provides accurate and
reliable short-circuit protection, adjustable current limiting, and
a delayed Power Good output that accommodates on-the-fly
output voltage changes requested by the CPU.
The device is specified over the commercial temperature range
of 0°C to 85°C and is available in a 28-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
PWM2
FB
PWM3
PWM4
SW1
CSSUM
CSCOMP
SW2
SW3
SW4
CSREF
PWM1
ADP3168
VID4
VID3
VID2
VID1
VID5
VID0
FBRTN
GND
EN
DELAY
ILIMIT
PWRGD
COMP
VCC
RT
RAMPADJ
CROWBAR
CURRENT
LIMIT
2-, 3-, 4-PHASE
DRIVER LOGIC
EN
SET
RESET
RESET
RESET
RESET
OSCILLATOR
CMP
CMP
CMP
CMP
CURRENT-
BALANCING
CIRCUIT
DELAY
UVLO
SHUTDOWN
AND BIAS
DAC
+150mV
DAC
–250mV
CSREF
PRECISION
REFERENCE
SOFT-
START
VID
DAC
EN
CURRENT-
LIMIT
CIRCUIT
0
19
11
12
15
10
28
13
14
26
8
25
24
23
17
18
22
21
20
16
1
2
3
4
6
5
7
9
27
Figure 1.