參數(shù)資料
型號: ADNS-6010
廠商: Avago Technologies Ltd.
英文描述: High Performance Laser Mouse Bundles
中文描述: 高性能激光鼠標捆綁
文件頁數(shù): 12/52頁
文件大?。?/td> 997K
代理商: ADNS-6010
12
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, V
DD3
=3.3V, fclk=24MHz.
Parameter
Symbol
Min.
Typ.
Max.
Units
VDD to RESET
t
OP
250
m
s
Notes
From VDD = 3.0V to RESET sampled
Data delay after
RESET
Input delay after
reset
Power Down
t
PU-RESET
180
ms
From RESET falling edge to valid motion data at 2000 fps
and shutter bound 20k.
From RESET falling edge to inputs active (NPD, MOSI,
NCS, SCLK)
From NPD falling edge to initiate the power down cycle
at 2000 fps (t
pd
= 1 frame period + 100
m
s )
From NPD rising edge to valid motion data at 2000 fps
and shutter bound 20k. Max assumes surface change
while NPD is low
From NPD rising edge to all registers contain data from
new images at 2000 fps (See Figure 11).
T
IN-RST
550
m
s
t
PD
600
m
s
Wake from NPD
t
PUPD
t
COMPUTE
75
ms
Data delay after
NPD
RESET pulse width
t
COMPUTE
3.1
ms
t
PW-RESET
10
m
s
MISO rise time
t
r-MISO
40
200
ns
C
L
= 50pF
MISO fall time
t
f-MISO
40
200
ns
C
L
= 50pF
MISO delay after
SCLK
MISO hold time
t
DLY-MISO
120
ns
From SCLK falling edge to MISO data valid, no load
conditions
Data held until next falling SCLK edge
t
hold-
MISO
t
hold-
MOSI
t
setup-
MOSI
t
SWW
250
ns
MOSI hold time
200
ns
Amount of time data is valid after SCLK rising edge
MOSI setup time
120
ns
From data valid to SCLK rising edge
SPI time between
write commands
SPI time between
write and read
commands
SPI time between
read and subse-
quent commands
50
m
s
From rising SCLK for last bit of the first data byte, to rising
SCLK for last bit of the second data byte.
From rising SCLK for last bit of the first data byte, to rising
SCLK for last bit of the second address byte.
t
SWR
50
m
s
t
SRW
t
SRR
250
ns
From rising SCLK for last bit of the first data byte, to fall-
ing SCLK for first bit of the second address byte.
SPI read address-
data delay
t
SRAD
50
m
s
From rising SCLK for last bit of the address byte, to falling
SCLK for first bit of data being read. All registers except
Motion & Motion_Burst
From rising SCLK for last bit of the address byte, to falling
SCLK for first bit of data being read. Applies to 0x02 Mo-
tion, and 0x50 Motion_Burst, registers
SPI motion read
address-data
delay
t
SRAD-
MOT
75
m
s
NCS to SCLK active
t
NCS-SCLK
120
ns
From NCS falling edge to first SCLK rising edge
SCLK to NCS inac-
tive
NCS to MISO
high-Z
PROM download
and frame capture
byte-to-byte delay
NCS to burst
mode exit
Transient Supply
Current
Input Capacitance
t
SCLK-NCS
120
ns
From last SCLK falling edge to NCS rising edge, for valid
MISO data transfer
From NCS rising edge to MISO high-Z state
t
NCS-MISO
250
ns
t
LOAD
10
m
s
(See Figure 24 and 25)
t
BEXIT
4
m
s
Time NCS must be held high to exit burst mode
I
DDT
68
mA
Max supply current during a VDD3 ramp from 0 to 3.6 V
C
IN
14-22
pF
OSC_IN, OSC_OUT
相關(guān)PDF資料
PDF描述
ADNS-6120 High Performance Laser Mouse Bundles
ADNS-6130-001 High Performance Laser Mouse Bundles
ADNS-6230-001 High Performance Laser Mouse Bundles
ADNV-6340 High Performance Laser Mouse Bundles
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