參數(shù)資料
型號(hào): ADN4694EBRZ-RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 4/20頁(yè)
文件大小: 0K
描述: IC TXRX MLVDS 100MBPS 8SOIC
標(biāo)準(zhǔn)包裝: 1,000
系列: *
ADN4690E/ADN4692E/ADN4694E/ADN4695E
Data Sheet
Rev. A | Page 12 of 20
DRIVER TIMING MEASUREMENTS
DI
NOTES
1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE < 2cm FROM DUT.
2. R1 IS 1%, METAL FILM, SURFACE MOUNT,
<2cm FROM DUT.
OUT
C1
1pF
C3
0.5pF
C2
1pF
10471-
022
R1
50
A/Y
B/Z
Figure 23. Driver Timing Measurement
DI
DE
S1
VCC
NOTES
1. C1, C2, C3, AND C4 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE < 2cm FROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT,
<2cm FROM DUT.
R1
24.9
C1
1pF
C2
1pF
C3
2.5pF
R2
24.9
10471-
023
C4
0.5pF
OUT
A/Y
B/Z
Figure 24. Driver Enable/Disable Time Test Circuit
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
50MHz; 50% ± 1% DUTY CYCLE.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
VCC/2
VCC
0V
1/f0
INPUT
(CLOCK)
10471-
024
0V
1/f0
OUTPUT
VA – VB
OR
VY – VZ
(IDEAL)
0V
tc(n)
tJ(PER) = |tc(n) – 1/f0|
OUTPUT
VA – VB
OR
VY – VZ
(ACTUAL)
Figure 25. Driver Period Jitter Characteristics
NOTES
1. INPUT PULSE GENERATOR: 1MHz; 50% ± 5% DUTY CYCLE;
tR, tF ≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
tPLH
tR
tF
tPHL
VCC
VSS
VPH
VPL
0% VSS
10% VSS
90% VSS
0V
OUT
DI
10471-
025
10% VSS
90% VSS
VCC/2
Figure 26. Driver Propagation, Rise/Fall Times and Voltage Overshoot
0.5VCC
VCC
0V
~ –0.6V
~ +0.6V
–0.1V
0.1V
DE
OUT
(DI = 0V)
OUT
(DI = VCC)
10471-
026
tPZH
tPZL
–0.1V
tPHZ
tPLZ
NOTES
1. INPUT PULSE GENERATOR: 1MHz; 50% ± 5% DUTY CYCLE;
tR, tF ≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
Figure 27. Driver Enable/Disable Times
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
100Mbps; 215 – 1PRBS.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
VA – VB
OR
VY – VZ
VA – VB
OR
VY – VZ
VCC
OUTPUT
INPUT
(PRBS)
0V
VCC/2
tJ(PP)
0V
VCC/2
10471-
027
Figure 28. Driver Peak-to-Peak Jitter Characteristics
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