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參數(shù)資料
型號: ADN4692EBRZ
廠商: Analog Devices Inc
文件頁數(shù): 16/20頁
文件大?。?/td> 0K
描述: IC INTERFACE TXRX
標(biāo)準(zhǔn)包裝: 56
系列: *
Data Sheet
ADN4690E/ADN4692E
Rev. 0 | Page 5 of 20
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions / Comments
DRIVER
Maximum Data Rate
100
Mbps
Propagation Delay
tPLH, tPHL
2
2.5
3.5
ns
Differential Output Rise/Fall Time
tR, tF
2
2.6
3.2
ns
Pulse Skew |tPHL tPLH|
tSK
30
150
ps
Part-to-Part Skew
tSK(PP)
0.9
ns
Period Jitter, rms (One Standard Deviation)2
tJ(PER)
2
3
ps
Peak-to-Peak Jitter2, 4
tJ(PP)
150
ps
100 Mbps 215 1 PRBS input,5
Disable Time from High Level
tPHZ
4
7
ns
Disable Time from Low Level
tPLZ
4
7
ns
Enable Time to High Level
tPZH
4
7
ns
Enable Time to Low Level
tPZL
4
7
ns
RECEIVER
Propagation Delay
tRPLH, tRPHL
2
6
ns
CL = 15 pF, see Figure 29, Figure 32
Rise/Fall Time
tR, tF
1
2.3
ns
CL = 15 pF, see Figure 29, Figure 32
Pulse Skew |tRPHL – tRPLH|
Type 1 Receiver (ADN4690E, ADN4692E)
tSK
100
300
ps
CL = 15 pF, see Figure 29, Figure 32
Part-to-Part Skew6
tSK(PP)
1
ns
CL = 15 pF, see Figure 29, Figure 32
Period Jitter, rms (One Standard Deviation)2
tJ(PER)
4
7
ps
Peak-to-Peak Jitter2, 4
Type 1 Receiver (ADN4690E, ADN4692E)
tJ(PP)
200
700
ps
100 Mbps 215 1 PRBS input,5 see
Disable Time from High Level
tRPHZ
6
10
ns
Disable Time from Low Level
tRPLZ
6
10
ns
Enable Time to High Level
tRPZH
10
15
ns
Enable Time to Low Level
tRPZL
10
15
ns
1 All typical values are given for VCC = 3.3 V and TA = 25°C.
2 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
3 tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
4 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).
5 tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
6 HP4194A impedance analyzer or equivalent.
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