
3.3 V, 200 Mbps, Half- and Full-Duplex,
High Speed M-LVDS Transceivers
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev.
A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2011–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rate: 200 Mbps (100 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types
for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch-free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: 1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
±15 kV HBM (human body model), air discharge
±8 kV HBM (human body model), contact discharge
±10 kV IEC 61000-4-2, air discharge
±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: 40°C to +85°C
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure
FUNCTIONAL BLOCK DIAGRAMS
ADN4691E/
ADN4696E
VCC
GND
RO
R
D
RE
DE
A
B
DI
10355-
001
Figure 1.
ADN4693E/
ADN4697E
VCC
GND
RO
R
D
RE
DE
DI
10355
-002
A
B
Z
Y
Figure 2.
GENERAL DESCRIPTION
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up to
200 Mbps (100 MHz). The receivers detect the bus state with a
differential input of as little as 50 mV over a common-mode
voltage range of 1 V to +3.4 V. ESD protection of up to ±15 kV
is implemented on the bus pins. The parts adhere to the
TIA/EIA-899 standard for M-LVDS and complement TIA/EIA-
644 LVDS devices with additional multipoint capabilities.
hysteresis, so that slow-changing signals or loss of input does
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the inputs are
open (open-circuit fail-safe).
The parts are available as half-duplex in an 8-lead SOIC package
for the ADN469xE parts is shown in
Table 1.
Table 1. ADN469xE Selection Table
Part No.
Receiver
Data Rate
SOIC
Duplex
Type 1
100 Mbps
8-lead
Half
Type 1
200 Mbps
8-lead
Half
Type 1
100 Mbps
14-lead
Full
Type 1
200 Mbps
14-lead
Full
Type 2
100 Mbps
8-lead
Half
Type 2
100 Mbps
14-lead
Full
Type 2
200 Mbps
8-lead
Half
Type 2
200 Mbps
14-lead
Full