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參數(shù)資料
| 型號： | ADN4670BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:10 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | LVDS |
| 輸出： | LVDS |
| 頻率 - 最大： | 1.1GHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ |
| 包裝： | 帶卷 (TR) |
ADN4670
Data Sheet
Rev. A | Page 8 of 12
THEORY OF OPERATION
The ADN4670 is a clock driver/expander for low voltage diffe-
rential signaling (LVDS). It takes a differential clock signal of
typically 350 mV and expands it to 10 differential clock outputs
with very low skew (typically < 30 ps). The device receives a
differential current signal from a source such as a twisted pair
cable, which develops a voltage of typically ±350 mV across a
100 terminating resistor. This signal passes via a differential
multiplexer to 10 drivers that each output a differential current
signal.
The device is programmable using a simple serial interface. One
of two differential clock inputs (CLK0/CLK0 or CLK1/ CLK1),
can be selected and any of the differential outputs (Q0/Q0 to
Q9/Q9) can be enabled or disabled.
LVDS RECIEVER INPUT TERMINATION
Terminate the clock inputs with 100 Ω resistors from CLK0
to CLK0 and CLK1 to /CLK1, placed as close as possible to
the input pins.
FAIL-SAFE OPERATION
In power-down mode (VDD = 0 V), the ADN4670 has fail-safe
input and output pins. In power-on mode, fail-safe biasing can
be achieved by connecting 10 k pull-up resistors from CLK0
and CLK1 to VDD and 10 k pull-down resistors from CLK0
and CLK1 to GND.
PROGRAMMING
Three control inputs are provided for programming the
ADN4670. EN is the enable input, which allows programming
when high, SI is the serial data input, and CK is the serial clock
input, which clocks data into the device on a low-to-high clock
transition. Each of these inputs has an internal pull-up or
pull-down resistor of 120 kΩ. EN and SI are pulled low if left
open-circuit while CK is pulled high.
The default condition if these inputs are left open-circuit is that
all outputs are enabled, and the state of SI selects the inputs (0 =
CLK0/CLK0 , 1 = CLK1/CLK1). This is the standard operating
mode for which no programming of the device is required.
Programming is enabled by taking EN high. The data on SI is
then clocked into the device on each 0-to-1 transition of CK.
Data on SI must be stable for the setup time (tSU) before the
clock transition and remain stable for the hold time (tH) after
the clock transition. To program the device, 11 bits of data are
needed, starting with Bit 0, which enables or disables outputs
Q9/Q9, through to Bit 10, which selects either CLK0/CLK0 or
CLK1/CLK1 as the inputs. A 12th clock pulse is then required
to transfer data from the shift register to the control register.
A low-to-high transition on EN resets the control register and
the next 12 CK pulses are programmed.
Table 5. Control Logic Truth Table
CK
EN
SI
CLK0
CLK1
Q0 to Q9
L
H
X
L
H
L
H
L
X
H
L
Open
X
L
H
L
H
X
L
H
L
H
L
H
X
H
L
H
L
H
X
Open
L
H
Table 6. State Machine Inputs
EN
SI
CK
Output
L
X
Default state with all outputs enabled, CLK0 selected, and the control register disabled
L
H
X
All outputs enabled, CLK1 selected, and the control register disabled
H
L
↑
First stage stores low, other stage stores data of previous stage
H
↑
First stage stores high, other stage stores data of previous stage
L
X
Reset the state machine, control register, and shift register
Table 7. Serial Input Sequence
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLK_SEL
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Table 8. Control Register
Bit 10
Bit[9:0]
Qx[9:0]
L
H
CLK0
H
CLK1
X
L
Outputs disabled
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