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參數(shù)資料
| 型號： | ADN4666ARUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 0K |
| 描述： | IC RCVR DIFF LVDS QUAD 16TSSOP |
| 標準包裝： | 96 |
| 類型： | 線路接收器 |
| 驅(qū)動器/接收器數(shù)： | 0/4 |
| 規(guī)程： | LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 管件 |
ADN4666
Rev. 0 | Page 7 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
RIN1+
RIN2+
RIN2–
EN
RIN4+
RIN3+
RIN3–
RIN1–
RIN4–
16
15
14
13
12
11
10
9
ROUT1
ROUT2
VCC
ROUT4
ROUT3
GND
ADN4666
TOP VIEW
(Not to Scale)
08
09
7-
0
6
EN
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RIN1
Receiver Channel 1 Inverting Input. When this input is more negative than RIN1+, ROUT1 is high. When this input is
more positive than RIN1+, ROUT1 is low.
2
RIN1+
Receiver Channel 1 Noninverting Input. When this input is more positive than RIN1, ROUT1 is high. When this input
is more negative than RIN1, ROUT1 is low.
3
ROUT1
Receiver Channel 1 Output (3 V TTL/CMOS). If the differential input voltage between RIN1+ and RIN1 is positive, this
output is high. If the differential input voltage is negative, this output is low.
4
EN
Active High Enable and Power-Down Input (3 V TTL/CMOS). When EN is low and EN is high, the receiver outputs
are disabled and are in a high impedance state. When EN is high and EN is low or when EN is low and EN is low,
the receiver outputs are enabled. When EN is high and EN is high, the receiver outputs are enabled.
5
ROUT2
Receiver Channel 2 Output (3 V TTL/CMOS). If the differential input voltage between RIN2+ and RIN2 is positive, this
output is high. If the differential input voltage is negative, this output is low.
6
RIN2+
Receiver Channel 2 Noninverting Input. When this input is more positive than RIN2, ROUT2 is high. When this input
is more negative than RIN2, ROUT2 is low.
7
RIN2
Receiver Channel 2 Inverting Input. When this input is more negative than RIN2+, ROUT2 is high. When this input is
more positive than RIN2+, ROUT2 is low.
8
GND
Ground Reference Point for All Circuitry on the Part.
9
RIN3
Receiver Channel 3 Inverting Input. When this input is more negative than RIN3+, ROUT3 is high. When this input is
more positive than RIN3+, ROUT3 is low.
10
RIN3+
Receiver Channel 3 Noninverting Input. When this input is more positive than RIN3, ROUT3 is high. When this input
is more negative than RIN3, ROUT3 is low.
11
ROUT3
Receiver Channel 3 Output (3 V TTL/CMOS). If the differential input voltage between RIN3+ and RIN3 is positive, this
output is high. If the differential input voltage is negative, this output is low.
12
EN
Active Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). ). When EN is low and EN is high, the
receiver outputs are disabled and are in a high impedance state. When EN is high and EN is low or when EN is low
and EN is low, the receiver outputs are enabled. When EN is high and EN is high, the receiver outputs are enabled.
13
ROUT4
Receiver Channel 4 Output (3 V TTL/CMOS). If the differential input voltage between RIN4+ and RIN4 is positive, this
output is high. If the differential input voltage is negative, this output is low.
14
RIN4+
Receiver Channel 4 Noninverting Input. When this input is more positive than RIN4, ROUT4 is high. When this input
is more negative than RIN4, ROUT4 is low.
15
RIN4
Receiver Channel 4 Inverting Input. When this input is more negative than RIN4+, ROUT4 is high. When this input is
more positive than RIN4+, ROUT4 is low.
16
VCC
Power Supply Input. The ADN4666 can be operated from 3.0 V to 3.6 V.
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