參數(shù)資料
型號： ADN2819ACPZ-CML-RL1
廠商： Analog Devices, Inc.
元件分類： 運(yùn)動控制電子
英文描述： Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
中文描述： 多速率為2.7 Gb / s的集成時鐘和數(shù)據(jù)恢復(fù)芯片限幅放大器
文件頁數(shù)： 11/24頁
文件大?。?/td> 570K
代理商： ADN2819ACPZ-CML-RL1
ADN2819
Rev. B | Page 11 of 24
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
–9.0
–9.5
–10.0
–8.5
1k
10k
100k
1M
100M
FREQUENCY (Hz)
10M
OC3_JIT_TOLERANCE
GBE_JIT_TOLERANCE
OC3_JIT_TRANSFER
GBE_JIT_TRANSFER
OC12_JIT_TOLERANCE
OC48_JIT_TOLERANCE
OC12_JIT_TRANSFER
OC48_JIT_TRANSFER
0
Figure 14. Jitter Transfer and Jitter Tracking BW
Table 4. Jitter Transfer and Tolerance: SONET Spec vs. ADN2819
Jitter Transfer
ADN2819
(kHz)
OC-48 2 MHz
590
OC-12
500 kHz
140
OC-3
130 kHz
48
Jitter Tolerance
SONET Spec
(UI p-p)
0.15
0.15
0.15
Rate
SONET Spec (f
C
)
Implementation
Margin
3.4
3.6
2.7
Mask Corner
Frequency
1 MHz
250 kHz
65 kHz
ADN2819
4.8 MHz
4.8 MHz
600 kHz
ADN2819
(UI p-p)
1.0
1.0
1.0
Implementation
Margin
1
6.67
6.67
6.67
1
Jitter tolerance measurements limited by test equipment capabilities.
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