參數(shù)資料
型號: ADN2811ACP-CML-RL
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字傳輸電路
英文描述: OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
中文描述: CLOCK RECOVERY CIRCUIT, QCC48
封裝: 7 X 7 MM, LEAD FREE, MO-220-VKKD-2, LFCSP-48
文件頁數(shù): 15/16頁
文件大?。?/td> 359K
代理商: ADN2811ACP-CML-RL
REV. A
ADN2811
–15–
50
50
ADN2811
0.1 F
NIN
PIN
50
TIA
VREF
VCC
50
Figure 21. ADN2811 with DC-Coupled Inputs
LOL Toggling during Loss of Input Data
If the input data stream is lost due to a break in the optical link
(or for any reason), the clock output from the ADN2811 will
stay within 1000 ppm of the VCO center frequency as long as
there is a valid reference clock. The LOL pin will toggle at a
rate of several kHz. This is because the LOL pin will toggle
between a Logic 1 and a Logic 0 while the frequency loop and
phase loop swap control of the VCO. The chain of events are as
follows:
The ADN2811 is locked to the input data stream; LOL = 0.
The input data stream is lost due to a break in the link. The
VCO frequency drifts until the frequency error is greater
than 1000 ppm. LOL is asserted to a Logic 1 as control of
the VCO is passed back to the frequency loop.
The frequency loop pulls the VCO to within 500 ppm of its
center frequency. Control of the VCO is passed back to the
phase loop and LOL is deasserted to a Logic 0.
The phase loop tries to acquire, but there is no input
data present so the VCO frequency drifts.
The VCO frequency drifts until the frequency error is
greater than 1000 ppm. LOL is asserted to a Logic 1 as
control of the VCO is passed back to the frequency
loop. This process is repeated until a valid input data
stream is re-established.
V
CM
= 0.4V MIN
(DC-COUPLED)
V
SE
= 5mV MIN
PIN
NIN
V p-p = PIN – NIN = 2 V
SE
= 10mV AT SENSITIVITY
INPUT (V)
Figure 22. Minimum Allowed DC-Coupled Input Levels
INPUT (V)
PIN
NIN
V
CM
= 0.6V
(DC-COUPLED)
V
SE
= 1.2V MAX
V p-p = PIN – NIN = 2 V
SE
= 2.4V MAX
Figure 23. Maximum Allowed DC-Coupled Input Levels
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