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參數(shù)資料
| 型號(hào)： | ADN2809XCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-DTL-38999 Series I; Body Material:Metal; Series:LJT; No. of Contacts:11; Connector Shell Size:21; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQCC48 |
| 封裝： | 7 X 7 MM, LFCSP-48 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大?。?/td> | 204K |
| 代理商： | ADN2809XCP |
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REV
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P
rB
Sept 2001
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106,
Norwood, MA 02062-9106 U
.
S
.
A
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Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
a
Preliminary Technical Data
Multi-Rate to 2.7Gbps Clock and Data
Recovery IC with Limiting Amplifier
ADN2809
FEATURES
Meets SONET Requirements for Jitter Transfer /
Generation / Tolerance
Quantizer Sensitivity: 6 mV typical
Adjustable Slice Level: +/- 100 mV
1.9GHz minimum Bandwidth
Loss of Signal Detect Range: 4mV to 17mV
Single Reference Clock Frequency for all rates
Including 15/14 (7%) Wrapper Rate
Choice of 19.44, 38.88, 77.76 or
155.52MHz
LVPECL / LVDS / LVCMOS / LVTTL compatible
inputs (LVPECL / LVDS only at 155.52 MHz)
19.44MHz Crystal Oscillator for Module apps
Loss of Lock indicator
Loopback mode for High Speed Test Data
Output Squelch & Clock Recovery Functions
Single Supply Operation: 3.3 Volts (+10%)
Low Power: 780 mW Typical
Patented Clock Recovery Architecture
7 x 7 mm 48 pin LFCSP
APPLICATIONS
SONET OC-3/12/48, SDH STM-1/4/16, and all
associated FEC rates
WDM transponders
SONET/SDH regenerators and test equipment
Backplane applications
PRODUCT DESCRIPTION
The ADN2809 provides the receiver functions of Quantization,
Signal Level Detect and Clock and Data Recovery at rates of
OC-3, OC-12, Gigabit Ethernet, OC-48 and all FEC rates. All
SONET jitter requirements are met, including: Jitter Transfer;
Jitter Generation; and Jitter Tolerance. All specifications are
quoted for -40 to 85C ambient temperature unless otherwise
noted.
The device is intended for WDM system applications and can be
used with either an external reference clock or an on-chip
oscillator crystal. Both native rates and 15/14 rate digital
‘wrappers’ rates are supported by the ADN2809, without any
change of reference clock required.
This device together with a PIN diode and a TIA preamplifier
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver front end Signal Detect circuit indicates when the
input signal level has fallen below a user adjustable threshold.
The ADN2809 is available in a compact 48 pin chip scale
package.
Functional Block Diagram
CF
Loss of lock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADN2809XCP-RL | Circular Connector; No. of Contacts:11; Series:LJT06R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:21-11 |
| ADN2820 | 10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| ADN2820ACHIPS | 10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| ADN2820S21 | 10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| ADNB-2012 | Optical Mouse Sensor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2809XCP-RL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier |
| ADN2811 | 制造商:AD 制造商全稱:Analog Devices 功能描述:OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2811ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADN2811ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
| ADN2811ACPZ-CML | 功能描述:IC CLK/DATA REC W/AMP 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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