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REV. 0
ADMCF340
–16–
In general, the on-times of the PWM signals in double update
mode are defined by:
T
AH
= (
PWMCHA
1
+
PWMCHA
2
–
PWMDT
1
–
PWMDT
2
)
×
T
CK
T
AL
= (
PWMTM
1
+
PWMTM
2
–
PWMCHA
1
–
PWMCHA
2
–
PWMDT
1
–
PWMDT
2
)
×
T
CK
d
T
T
PWMCHA
PWMTM
PWMCHA
PWMTM
PWMDT
PWMTM
PWMDT
PWMTM
d
T
T
PWMTM
PWMTM
PWMCHA
PWMTM
PWMTM
PWMCHA
PWMDT
+
1
PWMDT
PWMTM
PWMTM
AH
AH
S
AL
AL
S
=
=
+
+
+
+
=
=
+
+
(
)
+
+
+
(
)
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
2
–
because of the completely general case in double update mode,
the switching period is given by:
T
PWNMTM
PWMTM
T
S
CK
=
+
(
)
×
1
2
Again, the values of
T
AH
and
T
AL
are constrained to lie between
zero and
T
S
.
PWM signals similar to those illustrated in Figure 7 and Figure 8 can
be produced on the BH, BL, CH, and CL outputs by programming
the PWMCHB and PWMCHC Registers in a manner identical
to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
Registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If during initialization, the PWMTM Register is written
before the PWMCHA, PWMCHB, and PWMCHC Registers, the
first PWMSYNC pulse (and interrupt if enabled) will be generated
(1.5
×
T
CK
×
PWMTM) seconds after the initial write to the
PWMTM Register in single update mode. In double update mode,
the first PWMSYNC pulse will be generated (T
CK
×
PWMTM)
seconds after the initial write to the PWMTM Register in single
update mode.
Effective PWM Resolution
In single update mode, the same values of PWMCHA, PWMCHB,
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 T
CK
(or 100 ns for a 20 MHz
CLKOUT) since incrementing one of the duty cycle registers by
one changes the resultant on-time of the associated PWM signals
by T
CK
in each half period (or 2 T
CK
for the full period).
In double update mode, improved resolution is possible since
different values of the duty cycle registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of T
CK
. This corresponds to an effective
PWM resolution of T
CK
in double update mode (or 50 ns for a
20 MHz CLKOUT).
Table IV. Fundamental Characteristics of PWM Generation Unit of ADMCF340
16-BIT PWM TIMER
Parameter
Min
Typ
Max
Unit
Counter Resolution
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Dead Time Range
Programmable Dead Time Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth (T
CRST
)
Gate Drive Chop Frequency Range
16
100
50
Bits
ns
ns
μ
s
ns
μ
s
ns
Hz
μ
s
MHz
0
102
100
0
50
51
153
0.05
0.02
12.8
5